Lines Matching +full:pwm +full:- +full:map +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0-only
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * - the basic variant, called "orion-gpio", with the simplest
21 * non-SMP Discovery systems
22 * - the mv78200 variant for MV78200 Discovery systems. This variant
23 * turns the edge mask and level mask registers into CPU0 edge
24 * mask/level mask registers, and adds CPU1 edge mask/level mask
26 * - the armadaxp variant for Armada XP systems. This variant keeps
27 * the normal cause/edge mask/level mask registers when the global
28 * interrupts are used, but adds per-CPU cause/edge mask/level mask
29 * registers n a separate memory area for the per-CPU GPIO
49 #include <linux/pwm.h>
68 * PWM register offsets.
79 /* The MV78200 has per-CPU registers for edge mask and level mask */
84 * The Armada XP has per-CPU registers for interrupt cause, interrupt
85 * mask and interrupt level mask. Those are in percpu_regs range.
106 /* Used to preserve GPIO/PWM registers across suspend/resume */
121 /* Used for PWM support */
140 struct regmap **map, unsigned int *offset) in mvebu_gpioreg_edge_cause() argument
144 switch (mvchip->soc_variant) { in mvebu_gpioreg_edge_cause()
148 *map = mvchip->regs; in mvebu_gpioreg_edge_cause()
149 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset; in mvebu_gpioreg_edge_cause()
153 *map = mvchip->percpu_regs; in mvebu_gpioreg_edge_cause()
164 struct regmap *map; in mvebu_gpio_read_edge_cause() local
168 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); in mvebu_gpio_read_edge_cause()
169 regmap_read(map, offset, &val); in mvebu_gpio_read_edge_cause()
177 struct regmap *map; in mvebu_gpio_write_edge_cause() local
180 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); in mvebu_gpio_write_edge_cause()
181 regmap_write(map, offset, val); in mvebu_gpio_write_edge_cause()
186 struct regmap **map, unsigned int *offset) in mvebu_gpioreg_edge_mask() argument
190 switch (mvchip->soc_variant) { in mvebu_gpioreg_edge_mask()
193 *map = mvchip->regs; in mvebu_gpioreg_edge_mask()
194 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset; in mvebu_gpioreg_edge_mask()
198 *map = mvchip->regs; in mvebu_gpioreg_edge_mask()
203 *map = mvchip->percpu_regs; in mvebu_gpioreg_edge_mask()
214 struct regmap *map; in mvebu_gpio_read_edge_mask() local
218 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); in mvebu_gpio_read_edge_mask()
219 regmap_read(map, offset, &val); in mvebu_gpio_read_edge_mask()
227 struct regmap *map; in mvebu_gpio_write_edge_mask() local
230 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); in mvebu_gpio_write_edge_mask()
231 regmap_write(map, offset, val); in mvebu_gpio_write_edge_mask()
236 struct regmap **map, unsigned int *offset) in mvebu_gpioreg_level_mask() argument
240 switch (mvchip->soc_variant) { in mvebu_gpioreg_level_mask()
243 *map = mvchip->regs; in mvebu_gpioreg_level_mask()
244 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset; in mvebu_gpioreg_level_mask()
248 *map = mvchip->regs; in mvebu_gpioreg_level_mask()
253 *map = mvchip->percpu_regs; in mvebu_gpioreg_level_mask()
264 struct regmap *map; in mvebu_gpio_read_level_mask() local
268 mvebu_gpioreg_level_mask(mvchip, &map, &offset); in mvebu_gpio_read_level_mask()
269 regmap_read(map, offset, &val); in mvebu_gpio_read_level_mask()
277 struct regmap *map; in mvebu_gpio_write_level_mask() local
280 mvebu_gpioreg_level_mask(mvchip, &map, &offset); in mvebu_gpio_write_level_mask()
281 regmap_write(map, offset, val); in mvebu_gpio_write_level_mask()
286 * PWM controller.
290 return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF; in mvebu_pwmreg_blink_on_duration()
295 return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF; in mvebu_pwmreg_blink_off_duration()
305 return regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_set()
314 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); in mvebu_gpio_get()
319 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, in mvebu_gpio_get()
321 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_get()
325 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u); in mvebu_gpio_get()
336 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_blink()
353 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_direction_input()
376 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_direction_output()
387 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); in mvebu_gpio_get_direction()
399 return irq_create_mapping(mvchip->domain, pin); in mvebu_gpio_to_irq()
408 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_irq_ack()
409 u32 mask = d->mask; in mvebu_gpio_irq_ack() local
412 mvebu_gpio_write_edge_cause(mvchip, ~mask); in mvebu_gpio_irq_ack()
419 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_edge_irq_mask()
421 u32 mask = d->mask; in mvebu_gpio_edge_irq_mask() local
424 ct->mask_cache_priv &= ~mask; in mvebu_gpio_edge_irq_mask()
425 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_edge_irq_mask()
432 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_edge_irq_unmask()
434 u32 mask = d->mask; in mvebu_gpio_edge_irq_unmask() local
437 mvebu_gpio_write_edge_cause(mvchip, ~mask); in mvebu_gpio_edge_irq_unmask()
438 ct->mask_cache_priv |= mask; in mvebu_gpio_edge_irq_unmask()
439 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_edge_irq_unmask()
446 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_level_irq_mask()
448 u32 mask = d->mask; in mvebu_gpio_level_irq_mask() local
451 ct->mask_cache_priv &= ~mask; in mvebu_gpio_level_irq_mask()
452 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_level_irq_mask()
459 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_level_irq_unmask()
461 u32 mask = d->mask; in mvebu_gpio_level_irq_unmask() local
464 ct->mask_cache_priv |= mask; in mvebu_gpio_level_irq_unmask()
465 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_level_irq_unmask()
479 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
487 * EDGE cause mask
488 * data-in /--------| |-----| |----\
489 * -----| |----- ---- to main cause reg
490 * X \----------------| |----/
491 * polarity LEVEL mask
499 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_irq_set_type()
503 pin = d->hwirq; in mvebu_gpio_irq_set_type()
505 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); in mvebu_gpio_irq_set_type()
507 return -EINVAL; in mvebu_gpio_irq_set_type()
511 return -EINVAL; in mvebu_gpio_irq_set_type()
514 if (!(ct->type & type)) in mvebu_gpio_irq_set_type()
516 return -EINVAL; in mvebu_gpio_irq_set_type()
524 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
525 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
530 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
531 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
537 regmap_read(mvchip->regs, in mvebu_gpio_irq_set_type()
538 GPIO_IN_POL_OFF + mvchip->offset, &in_pol); in mvebu_gpio_irq_set_type()
539 regmap_read(mvchip->regs, in mvebu_gpio_irq_set_type()
540 GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_irq_set_type()
550 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
551 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
571 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_irq_handler()
578 for (i = 0; i < mvchip->chip.ngpio; i++) { in mvebu_gpio_irq_handler()
581 irq = irq_find_mapping(mvchip->domain, i); in mvebu_gpio_irq_handler()
591 regmap_read(mvchip->regs, in mvebu_gpio_irq_handler()
592 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_handler()
595 regmap_write(mvchip->regs, in mvebu_gpio_irq_handler()
596 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_handler()
621 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) in mvebu_pwm_request() argument
624 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_request()
629 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_request()
631 if (mvpwm->gpiod) { in mvebu_pwm_request()
632 ret = -EBUSY; in mvebu_pwm_request()
634 desc = gpiochip_request_own_desc(&mvchip->chip, in mvebu_pwm_request()
635 pwm->hwpwm, "mvebu-pwm", in mvebu_pwm_request()
643 mvpwm->gpiod = desc; in mvebu_pwm_request()
646 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_request()
650 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) in mvebu_pwm_free() argument
655 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_free()
656 gpiochip_free_own_desc(mvpwm->gpiod); in mvebu_pwm_free()
657 mvpwm->gpiod = NULL; in mvebu_pwm_free()
658 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_free()
662 struct pwm_device *pwm, in mvebu_pwm_get_state() argument
667 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_get_state()
672 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_get_state()
674 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u); in mvebu_pwm_get_state()
680 state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, in mvebu_pwm_get_state()
681 mvpwm->clk_rate); in mvebu_pwm_get_state()
683 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u); in mvebu_pwm_get_state()
689 state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate); in mvebu_pwm_get_state()
691 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u); in mvebu_pwm_get_state()
693 state->enabled = true; in mvebu_pwm_get_state()
695 state->enabled = false; in mvebu_pwm_get_state()
697 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_get_state()
702 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in mvebu_pwm_apply() argument
706 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_apply()
711 if (state->polarity != PWM_POLARITY_NORMAL) in mvebu_pwm_apply()
712 return -EINVAL; in mvebu_pwm_apply()
714 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; in mvebu_pwm_apply()
717 return -EINVAL; in mvebu_pwm_apply()
729 val = (unsigned long long) mvpwm->clk_rate * state->period; in mvebu_pwm_apply()
731 val -= on; in mvebu_pwm_apply()
733 return -EINVAL; in mvebu_pwm_apply()
741 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_apply()
743 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on); in mvebu_pwm_apply()
744 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off); in mvebu_pwm_apply()
745 if (state->enabled) in mvebu_pwm_apply()
746 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); in mvebu_pwm_apply()
748 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); in mvebu_pwm_apply()
750 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_apply()
764 struct mvebu_pwm *mvpwm = mvchip->mvpwm; in mvebu_pwm_suspend()
766 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, in mvebu_pwm_suspend()
767 &mvpwm->blink_select); in mvebu_pwm_suspend()
768 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), in mvebu_pwm_suspend()
769 &mvpwm->blink_on_duration); in mvebu_pwm_suspend()
770 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), in mvebu_pwm_suspend()
771 &mvpwm->blink_off_duration); in mvebu_pwm_suspend()
776 struct mvebu_pwm *mvpwm = mvchip->mvpwm; in mvebu_pwm_resume()
778 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, in mvebu_pwm_resume()
779 mvpwm->blink_select); in mvebu_pwm_resume()
780 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), in mvebu_pwm_resume()
781 mvpwm->blink_on_duration); in mvebu_pwm_resume()
782 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), in mvebu_pwm_resume()
783 mvpwm->blink_off_duration); in mvebu_pwm_resume()
790 struct device *dev = &pdev->dev; in mvebu_pwm_probe()
797 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { in mvebu_pwm_probe()
798 int ret = device_property_read_u32(dev, "marvell,pwm-offset", in mvebu_pwm_probe()
804 * There are only two sets of PWM configuration registers for in mvebu_pwm_probe()
809 if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm")) in mvebu_pwm_probe()
814 if (IS_ERR(mvchip->clk)) in mvebu_pwm_probe()
815 return PTR_ERR(mvchip->clk); in mvebu_pwm_probe()
817 chip = devm_pwmchip_alloc(dev, mvchip->chip.ngpio, sizeof(*mvpwm)); in mvebu_pwm_probe()
822 mvchip->mvpwm = mvpwm; in mvebu_pwm_probe()
823 mvpwm->mvchip = mvchip; in mvebu_pwm_probe()
824 mvpwm->offset = offset; in mvebu_pwm_probe()
826 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { in mvebu_pwm_probe()
827 mvpwm->regs = mvchip->regs; in mvebu_pwm_probe()
829 switch (mvchip->offset) { in mvebu_pwm_probe()
838 mvpwm->offset += PWM_BLINK_COUNTER_B_OFF; in mvebu_pwm_probe()
841 return -EINVAL; in mvebu_pwm_probe()
844 base = devm_platform_ioremap_resource_byname(pdev, "pwm"); in mvebu_pwm_probe()
848 mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base, in mvebu_pwm_probe()
850 if (IS_ERR(mvpwm->regs)) in mvebu_pwm_probe()
851 return PTR_ERR(mvpwm->regs); in mvebu_pwm_probe()
855 * with id 1. Don't allow further GPIO chips to be used for PWM. in mvebu_pwm_probe()
862 return -EINVAL; in mvebu_pwm_probe()
865 regmap_write(mvchip->regs, in mvebu_pwm_probe()
866 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set); in mvebu_pwm_probe()
868 mvpwm->clk_rate = clk_get_rate(mvchip->clk); in mvebu_pwm_probe()
869 if (!mvpwm->clk_rate) { in mvebu_pwm_probe()
871 return -EINVAL; in mvebu_pwm_probe()
874 chip->ops = &mvebu_pwm_ops; in mvebu_pwm_probe()
876 spin_lock_init(&mvpwm->lock); in mvebu_pwm_probe()
891 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out); in mvebu_gpio_dbg_show()
892 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf); in mvebu_gpio_dbg_show()
893 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink); in mvebu_gpio_dbg_show()
894 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol); in mvebu_gpio_dbg_show()
895 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_dbg_show()
907 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); in mvebu_gpio_dbg_show()
916 seq_printf(s, " in %s (act %s) - IRQ", in mvebu_gpio_dbg_show()
936 .compatible = "marvell,orion-gpio",
940 .compatible = "marvell,mv78200-gpio",
944 .compatible = "marvell,armadaxp-gpio",
948 .compatible = "marvell,armada-370-gpio",
952 .compatible = "marvell,armada-8k-gpio",
965 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_suspend()
966 &mvchip->out_reg); in mvebu_gpio_suspend()
967 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_suspend()
968 &mvchip->io_conf_reg); in mvebu_gpio_suspend()
969 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_suspend()
970 &mvchip->blink_en_reg); in mvebu_gpio_suspend()
971 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_suspend()
972 &mvchip->in_pol_reg); in mvebu_gpio_suspend()
974 switch (mvchip->soc_variant) { in mvebu_gpio_suspend()
977 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, in mvebu_gpio_suspend()
978 &mvchip->edge_mask_regs[0]); in mvebu_gpio_suspend()
979 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, in mvebu_gpio_suspend()
980 &mvchip->level_mask_regs[0]); in mvebu_gpio_suspend()
984 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
986 &mvchip->edge_mask_regs[i]); in mvebu_gpio_suspend()
987 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
989 &mvchip->level_mask_regs[i]); in mvebu_gpio_suspend()
994 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
996 &mvchip->edge_mask_regs[i]); in mvebu_gpio_suspend()
997 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
999 &mvchip->level_mask_regs[i]); in mvebu_gpio_suspend()
1017 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_resume()
1018 mvchip->out_reg); in mvebu_gpio_resume()
1019 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_resume()
1020 mvchip->io_conf_reg); in mvebu_gpio_resume()
1021 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_resume()
1022 mvchip->blink_en_reg); in mvebu_gpio_resume()
1023 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_resume()
1024 mvchip->in_pol_reg); in mvebu_gpio_resume()
1026 switch (mvchip->soc_variant) { in mvebu_gpio_resume()
1029 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, in mvebu_gpio_resume()
1030 mvchip->edge_mask_regs[0]); in mvebu_gpio_resume()
1031 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, in mvebu_gpio_resume()
1032 mvchip->level_mask_regs[0]); in mvebu_gpio_resume()
1036 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1038 mvchip->edge_mask_regs[i]); in mvebu_gpio_resume()
1039 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1041 mvchip->level_mask_regs[i]); in mvebu_gpio_resume()
1046 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1048 mvchip->edge_mask_regs[i]); in mvebu_gpio_resume()
1049 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1051 mvchip->level_mask_regs[i]); in mvebu_gpio_resume()
1073 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base, in mvebu_gpio_probe_raw()
1075 if (IS_ERR(mvchip->regs)) in mvebu_gpio_probe_raw()
1076 return PTR_ERR(mvchip->regs); in mvebu_gpio_probe_raw()
1082 mvchip->offset = 0; in mvebu_gpio_probe_raw()
1086 * per-CPU registers in mvebu_gpio_probe_raw()
1088 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { in mvebu_gpio_probe_raw()
1093 mvchip->percpu_regs = in mvebu_gpio_probe_raw()
1094 devm_regmap_init_mmio(&pdev->dev, base, in mvebu_gpio_probe_raw()
1096 if (IS_ERR(mvchip->percpu_regs)) in mvebu_gpio_probe_raw()
1097 return PTR_ERR(mvchip->percpu_regs); in mvebu_gpio_probe_raw()
1106 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node); in mvebu_gpio_probe_syscon()
1107 if (IS_ERR(mvchip->regs)) in mvebu_gpio_probe_syscon()
1108 return PTR_ERR(mvchip->regs); in mvebu_gpio_probe_syscon()
1110 if (device_property_read_u32(&pdev->dev, "offset", &mvchip->offset)) in mvebu_gpio_probe_syscon()
1111 return -EINVAL; in mvebu_gpio_probe_syscon()
1126 struct device_node *np = pdev->dev.of_node; in mvebu_gpio_probe()
1135 soc_variant = (unsigned long)device_get_match_data(&pdev->dev); in mvebu_gpio_probe()
1144 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), in mvebu_gpio_probe()
1147 return -ENOMEM; in mvebu_gpio_probe()
1151 if (device_property_read_u32(&pdev->dev, "ngpios", &ngpios)) { in mvebu_gpio_probe()
1152 dev_err(&pdev->dev, "Missing ngpios OF property\n"); in mvebu_gpio_probe()
1153 return -ENODEV; in mvebu_gpio_probe()
1156 id = of_alias_get_id(pdev->dev.of_node, "gpio"); in mvebu_gpio_probe()
1158 dev_err(&pdev->dev, "Couldn't get OF id\n"); in mvebu_gpio_probe()
1162 mvchip->clk = devm_clk_get(&pdev->dev, NULL); in mvebu_gpio_probe()
1164 if (!IS_ERR(mvchip->clk)) in mvebu_gpio_probe()
1165 clk_prepare_enable(mvchip->clk); in mvebu_gpio_probe()
1167 mvchip->soc_variant = soc_variant; in mvebu_gpio_probe()
1168 mvchip->chip.label = dev_name(&pdev->dev); in mvebu_gpio_probe()
1169 mvchip->chip.parent = &pdev->dev; in mvebu_gpio_probe()
1170 mvchip->chip.request = gpiochip_generic_request; in mvebu_gpio_probe()
1171 mvchip->chip.free = gpiochip_generic_free; in mvebu_gpio_probe()
1172 mvchip->chip.get_direction = mvebu_gpio_get_direction; in mvebu_gpio_probe()
1173 mvchip->chip.direction_input = mvebu_gpio_direction_input; in mvebu_gpio_probe()
1174 mvchip->chip.get = mvebu_gpio_get; in mvebu_gpio_probe()
1175 mvchip->chip.direction_output = mvebu_gpio_direction_output; in mvebu_gpio_probe()
1176 mvchip->chip.set_rv = mvebu_gpio_set; in mvebu_gpio_probe()
1178 mvchip->chip.to_irq = mvebu_gpio_to_irq; in mvebu_gpio_probe()
1179 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; in mvebu_gpio_probe()
1180 mvchip->chip.ngpio = ngpios; in mvebu_gpio_probe()
1181 mvchip->chip.can_sleep = false; in mvebu_gpio_probe()
1182 mvchip->chip.dbg_show = mvebu_gpio_dbg_show; in mvebu_gpio_probe()
1193 * Mask and clear GPIO interrupts. in mvebu_gpio_probe()
1198 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1199 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1200 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1201 GPIO_EDGE_MASK_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1202 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1203 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1206 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); in mvebu_gpio_probe()
1208 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1210 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1215 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); in mvebu_gpio_probe()
1216 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0); in mvebu_gpio_probe()
1217 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0); in mvebu_gpio_probe()
1219 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1221 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1223 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1231 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); in mvebu_gpio_probe()
1233 /* Some MVEBU SoCs have simple PWM support for GPIO lines */ in mvebu_gpio_probe()
1244 mvchip->domain = in mvebu_gpio_probe()
1246 if (!mvchip->domain) { in mvebu_gpio_probe()
1247 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", in mvebu_gpio_probe()
1248 mvchip->chip.label); in mvebu_gpio_probe()
1249 return -ENODEV; in mvebu_gpio_probe()
1252 err = devm_add_action_or_reset(&pdev->dev, mvebu_gpio_remove_irq_domain, in mvebu_gpio_probe()
1253 mvchip->domain); in mvebu_gpio_probe()
1258 mvchip->domain, ngpios, 2, np->name, handle_level_irq, in mvebu_gpio_probe()
1261 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", in mvebu_gpio_probe()
1262 mvchip->chip.label); in mvebu_gpio_probe()
1268 * access to the mask registers in mvebu_gpio_probe()
1270 gc = irq_get_domain_generic_chip(mvchip->domain, 0); in mvebu_gpio_probe()
1271 gc->private = mvchip; in mvebu_gpio_probe()
1272 ct = &gc->chip_types[0]; in mvebu_gpio_probe()
1273 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; in mvebu_gpio_probe()
1274 ct->chip.irq_mask = mvebu_gpio_level_irq_mask; in mvebu_gpio_probe()
1275 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; in mvebu_gpio_probe()
1276 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; in mvebu_gpio_probe()
1277 ct->chip.name = mvchip->chip.label; in mvebu_gpio_probe()
1279 ct = &gc->chip_types[1]; in mvebu_gpio_probe()
1280 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; in mvebu_gpio_probe()
1281 ct->chip.irq_ack = mvebu_gpio_irq_ack; in mvebu_gpio_probe()
1282 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; in mvebu_gpio_probe()
1283 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; in mvebu_gpio_probe()
1284 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; in mvebu_gpio_probe()
1285 ct->handler = handle_edge_irq; in mvebu_gpio_probe()
1286 ct->chip.name = mvchip->chip.label; in mvebu_gpio_probe()
1307 .name = "mvebu-gpio",