Lines Matching +full:pwm +full:- +full:map +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0
3 * Pinctrl driver for the T-Head TH1520 SoC
26 #include <linux/pinctrl/pinconf-generic.h>
67 return thp->base + 4 * (pin / 2); in th1520_padcfg()
78 return thp->base + 0x400 + 4 * (pin / 8); in th1520_muxcfg()
115 [TH1520_MUX_PWM] = "pwm",
284 TH1520_PAD(2, QSPI0_SCLK, QSPI, PWM, I2S, GPIO, ____, ____, 0),
285 TH1520_PAD(3, QSPI0_CSN0, QSPI, PWM, I2S, GPIO, ____, ____, 0),
286 TH1520_PAD(4, QSPI0_CSN1, QSPI, PWM, I2S, GPIO, ____, ____, 0),
287 TH1520_PAD(5, QSPI0_D0_MOSI, QSPI, PWM, I2S, GPIO, ____, ____, 0),
288 TH1520_PAD(6, QSPI0_D1_MISO, QSPI, PWM, I2S, GPIO, ____, ____, 0),
289 TH1520_PAD(7, QSPI0_D2_WP, QSPI, PWM, I2S, GPIO, ____, ____, 0),
316 TH1520_PAD(34, GPIO3_2, GPIO, PWM, ____, ____, ____, ____, 0),
317 TH1520_PAD(35, GPIO3_3, GPIO, PWM, ____, ____, ____, ____, 0),
318 TH1520_PAD(36, HDMI_SCL, HDMI, PWM, ____, GPIO, ____, ____, 0),
319 TH1520_PAD(37, HDMI_SDA, HDMI, PWM, ____, GPIO, ____, ____, 0),
335 TH1520_PAD(53, GMAC0_COL, MAC0, PWM, ____, GPIO, ____, ____, 0),
336 TH1520_PAD(54, GMAC0_CRS, MAC0, PWM, ____, GPIO, ____, ____, 0),
340 .name = "th1520-group1",
346 .name = "th1520-group2",
352 .name = "th1520-group3",
361 return thp->desc.npins; in th1520_pinctrl_get_groups_count()
369 return thp->desc.pins[gsel].name; in th1520_pinctrl_get_group_name()
379 *pins = &thp->desc.pins[gsel].number; in th1520_pinctrl_get_group_pins()
394 scoped_guard(raw_spinlock_irqsave, &thp->lock) { in th1520_pin_dbg_show()
408 struct pinctrl_map *map, unsigned int nmaps) in th1520_pinctrl_dt_free_map() argument
414 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN && in th1520_pinctrl_dt_free_map()
415 map[i].data.configs.configs != seen) { in th1520_pinctrl_dt_free_map()
416 seen = map[i].data.configs.configs; in th1520_pinctrl_dt_free_map()
421 kfree(map); in th1520_pinctrl_dt_free_map()
430 struct pinctrl_map *map; in th1520_pinctrl_dt_node_to_map() local
441 dev_err(thp->pctl->dev, "no pins selected for %pOFn.%pOFn\n", in th1520_pinctrl_dt_node_to_map()
443 return -EINVAL; in th1520_pinctrl_dt_node_to_map()
450 map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL); in th1520_pinctrl_dt_node_to_map()
451 if (!map) in th1520_pinctrl_dt_node_to_map()
452 return -ENOMEM; in th1520_pinctrl_dt_node_to_map()
455 guard(mutex)(&thp->mutex); in th1520_pinctrl_dt_node_to_map()
467 dev_err(thp->pctl->dev, "%pOFn.%pOFn: error parsing pin config\n", in th1520_pinctrl_dt_node_to_map()
475 dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown function '%s'\n", in th1520_pinctrl_dt_node_to_map()
477 ret = -EINVAL; in th1520_pinctrl_dt_node_to_map()
481 funcname = devm_kasprintf(thp->pctl->dev, GFP_KERNEL, "%pOFn.%pOFn", in th1520_pinctrl_dt_node_to_map()
484 ret = -ENOMEM; in th1520_pinctrl_dt_node_to_map()
489 pgnames = devm_kcalloc(thp->pctl->dev, npins, sizeof(*pgnames), GFP_KERNEL); in th1520_pinctrl_dt_node_to_map()
491 ret = -ENOMEM; in th1520_pinctrl_dt_node_to_map()
502 for (i = 0; i < thp->desc.npins; i++) { in th1520_pinctrl_dt_node_to_map()
503 if (!strcmp(pinname, thp->desc.pins[i].name)) in th1520_pinctrl_dt_node_to_map()
506 if (i == thp->desc.npins) { in th1520_pinctrl_dt_node_to_map()
508 dev_err(thp->pctl->dev, "%pOFn.%pOFn: unknown pin '%s'\n", in th1520_pinctrl_dt_node_to_map()
510 ret = -EINVAL; in th1520_pinctrl_dt_node_to_map()
515 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_PIN; in th1520_pinctrl_dt_node_to_map()
516 map[nmaps].data.configs.group_or_pin = thp->desc.pins[i].name; in th1520_pinctrl_dt_node_to_map()
517 map[nmaps].data.configs.configs = configs; in th1520_pinctrl_dt_node_to_map()
518 map[nmaps].data.configs.num_configs = nconfigs; in th1520_pinctrl_dt_node_to_map()
522 pgnames[npins++] = thp->desc.pins[i].name; in th1520_pinctrl_dt_node_to_map()
523 map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP; in th1520_pinctrl_dt_node_to_map()
524 map[nmaps].data.mux.function = funcname; in th1520_pinctrl_dt_node_to_map()
525 map[nmaps].data.mux.group = thp->desc.pins[i].name; in th1520_pinctrl_dt_node_to_map()
534 dev_err(thp->pctl->dev, "error adding function %s\n", funcname); in th1520_pinctrl_dt_node_to_map()
540 *maps = map; in th1520_pinctrl_dt_node_to_map()
547 th1520_pinctrl_dt_free_map(pctldev, map, nmaps); in th1520_pinctrl_dt_node_to_map()
576 u32 mask, u32 value) in th1520_padcfg_rmw() argument
582 mask <<= shift; in th1520_padcfg_rmw()
585 scoped_guard(raw_spinlock_irqsave, &thp->lock) { in th1520_padcfg_rmw()
587 tmp = (tmp & ~mask) | value; in th1520_padcfg_rmw()
603 if (th1520_pad_no_padcfg(desc->drv_data)) in th1520_pinconf_get()
604 return -ENOTSUPP; in th1520_pinconf_get()
649 return -ENOTSUPP; in th1520_pinconf_get()
653 return enabled ? 0 : -EINVAL; in th1520_pinconf_get()
660 unsigned int pin = thp->desc.pins[gsel].number; in th1520_pinconf_group_get()
671 u16 mask, value; in th1520_pinconf_set() local
673 if (th1520_pad_no_padcfg(desc->drv_data)) in th1520_pinconf_set()
674 return -ENOTSUPP; in th1520_pinconf_set()
676 mask = 0; in th1520_pinconf_set()
684 mask |= TH1520_PADCFG_BIAS; in th1520_pinconf_set()
689 return -ENOTSUPP; in th1520_pinconf_set()
690 mask |= TH1520_PADCFG_BIAS; in th1520_pinconf_set()
696 return -ENOTSUPP; in th1520_pinconf_set()
697 mask |= TH1520_PADCFG_BIAS; in th1520_pinconf_set()
705 mask |= TH1520_PADCFG_DS; in th1520_pinconf_set()
710 mask |= TH1520_PADCFG_IE; in th1520_pinconf_set()
717 mask |= TH1520_PADCFG_ST; in th1520_pinconf_set()
724 mask |= TH1520_PADCFG_SL; in th1520_pinconf_set()
731 return -ENOTSUPP; in th1520_pinconf_set()
735 return th1520_padcfg_rmw(thp, pin, mask, value); in th1520_pinconf_set()
744 unsigned int pin = thp->desc.pins[gsel].number; in th1520_pinconf_group_set()
778 u32 mask, value, tmp; in th1520_pinmux_set() local
785 dev_err(thp->pctl->dev, "invalid mux %s for pin %s\n", in th1520_pinmux_set()
786 th1520_muxtype_string[muxtype], pin_get_name(thp->pctl, pin)); in th1520_pinmux_set()
787 return -EINVAL; in th1520_pinmux_set()
790 mask = GENMASK(3, 0) << shift; in th1520_pinmux_set()
793 scoped_guard(raw_spinlock_irqsave, &thp->lock) { in th1520_pinmux_set()
795 tmp = (tmp & ~mask) | value; in th1520_pinmux_set()
809 return -EINVAL; in th1520_pinmux_set_mux()
811 muxtype = (uintptr_t)func->data; in th1520_pinmux_set_mux()
812 return th1520_pinmux_set(thp, thp->desc.pins[gsel].number, in th1520_pinmux_set_mux()
813 th1520_pad_muxdata(thp->desc.pins[gsel].drv_data), in th1520_pinmux_set_mux()
825 th1520_pad_muxdata(desc->drv_data), in th1520_gpio_request_enable()
851 struct device *dev = &pdev->dev; in th1520_pinctrl_probe()
853 struct device_node *np = dev->of_node; in th1520_pinctrl_probe()
861 return -ENOMEM; in th1520_pinctrl_probe()
863 thp->base = devm_platform_ioremap_resource(pdev, 0); in th1520_pinctrl_probe()
864 if (IS_ERR(thp->base)) in th1520_pinctrl_probe()
865 return PTR_ERR(thp->base); in th1520_pinctrl_probe()
871 ret = of_property_read_u32(np, "thead,pad-group", &pin_group); in th1520_pinctrl_probe()
873 return dev_err_probe(dev, ret, "failed to read the thead,pad-group property\n"); in th1520_pinctrl_probe()
882 return dev_err_probe(dev, -EINVAL, "unit address did not match any pad group\n"); in th1520_pinctrl_probe()
884 thp->desc.name = group->name; in th1520_pinctrl_probe()
885 thp->desc.pins = group->pins; in th1520_pinctrl_probe()
886 thp->desc.npins = group->npins; in th1520_pinctrl_probe()
887 thp->desc.pctlops = &th1520_pinctrl_ops; in th1520_pinctrl_probe()
888 thp->desc.pmxops = &th1520_pinmux_ops; in th1520_pinctrl_probe()
889 thp->desc.confops = &th1520_pinconf_ops; in th1520_pinctrl_probe()
890 thp->desc.owner = THIS_MODULE; in th1520_pinctrl_probe()
891 mutex_init(&thp->mutex); in th1520_pinctrl_probe()
892 raw_spin_lock_init(&thp->lock); in th1520_pinctrl_probe()
894 ret = devm_pinctrl_register_and_init(dev, &thp->desc, thp, &thp->pctl); in th1520_pinctrl_probe()
898 return pinctrl_enable(thp->pctl); in th1520_pinctrl_probe()
902 { .compatible = "thead,th1520-pinctrl"},
910 .name = "pinctrl-th1520",
916 MODULE_DESCRIPTION("Pinctrl driver for the T-Head TH1520 SoC");