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/qemu/docs/devel/migration/
H A Dqpl-compression.rst4 The Intel Query Processing Library (Intel ``QPL``) is an open-source library to
8 The ``QPL`` compression relies on Intel In-Memory Analytics Accelerator(``IAA``)
21 +----------------+ +------------------+
22 | MultiFD Thread | |accel-config tool |
23 +-------+--------+ +--------+---------+
27 +-------+--------+ | Setup IAA
29 +-------+---+----+ |
31 | +-------------+-------+
33 | Devices +-----+-----+
35 | +-----+-----+
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/qemu/docs/devel/testing/
H A Dblkdebug.rst5 Copyright (C) 2014-2015 Red Hat Inc
8 the COPYING file in the top-level directory.
10 The ``blkdebug`` block driver is a rule-based error injection engine. It can be
17 ----------
20 while updating tables happen halfway through request processing and require
27 -----
29 engine when to fail an I/O request.
35 follows the same .ini-like format used by QEMU's ``-readconfig`` option, and
41 [inject-error]
47 ``/usr/include/asm-generic/errno-base.h`` for errno values.
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/qemu/docs/specs/
H A Dppc-xive.rst7 Engine".
19 The XIVE IC is composed of three sub-engines, each taking care of a
20 processing layer of external interrupts:
22 - Interrupt Virtualization Source Engine (IVSE), or Source Controller
25 controller for the core IPIs and other sub-chips (NX, CAP, NPU) of
28 - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
32 - Interrupt Virtualization Presentation Engine (IVPE) or Presentation
40 +------------------------------------+ IPIs
41 | +---------+ +---------+ +--------+ | +-------+
42 | |IVRE | |Common Q | |IVPE |----> | CORES |
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/qemu/docs/system/arm/
H A Dxlnx-versal-virt.rst1 Xilinx Versal Virt (``xlnx-versal-virt``)
4 Xilinx Versal is a family of heterogeneous multi-core SoCs
6 peripherals in a Processing System (PS) with runtime programmable
7 FPGA logic (PL) and an Artificial Intelligence Engine (AIE).
10 https://www.xilinx.com/products/silicon-devices/acap/versal.html
22 - 2 ACPUs (ARM Cortex-A72)
26 - Interrupt controller (ARM GICv3)
27 - 2 UARTs (ARM PL011)
28 - An RTC (Versal built-in)
29 - 2 GEMs (Cadence MACB Ethernet MACs)
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/qemu/include/block/
H A Daio.h10 * the COPYING file in the top-level directory.
20 #include "qemu/coroutine-core.h"
26 #include "block/graph-lock.h"
27 #include "hw/qdev-core.h"
76 * Called with ctx->list_lock acquired.
88 * Called with ctx->list_lock incremented but not locked.
98 * Tell aio_poll() when to stop userspace polling early because ->wait()
106 * Returns: true if ->wait() should be called, false otherwise.
133 /* Used by AioContext users to protect from multi-threaded access. */
144 /* The list of registered AIO handlers. Protected by ctx->list_lock. */
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/qemu/audio/
H A Dmixeng.c2 * QEMU Mixing engine
4 * Copyright (c) 2004-2005 Vassili Karpov (malc)
27 #include "qemu/error-report.h"
274 /* macros to map [-1.f, 1.f] <-> [INT32_MIN, INT32_MAX + 1] */
296 while (samples--) { in conv_natural_float_to_mono()
297 dst->r = dst->l = CONV_NATURAL_FLOAT(*in++); in conv_natural_float_to_mono()
307 while (samples--) { in conv_swap_float_to_mono()
308 dst->r = dst->l = CONV_NATURAL_FLOAT(F32S_TO_F32(*in_f32s++)); in conv_swap_float_to_mono()
318 while (samples--) { in conv_natural_float_to_stereo()
319 dst->l = CONV_NATURAL_FLOAT(*in++); in conv_natural_float_to_stereo()
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/qemu/hw/ssi/
H A Dpnv_spi.c6 * SPDX-License-Identifier: GPL-2.0-or-later
11 #include "hw/qdev-properties.h"
46 uint16_t rdr_match_mask = GETFIELD(SPI_MM_RDR_MATCH_MASK, s->regs[SPI_MM_REG]); in does_rdr_match()
47 uint16_t rdr_match_val = GETFIELD(SPI_MM_RDR_MATCH_VAL, s->regs[SPI_MM_REG]); in does_rdr_match()
50 GETFIELD(PPC_BITMASK(48, 63), s->regs[SPI_RCV_DATA_REG]))) { in does_rdr_match()
61 * Offset is an index between 0 and PNV_SPI_REG_SIZE - 1 in get_from_offset()
65 byte = (s->regs[SPI_XMIT_DATA_REG] >> (56 - offset * 8)) & 0xFF; in get_from_offset()
89 } else if (!fifo8_is_empty(&s->rx_fifo)) { in read_from_frame()
90 byte = fifo8_pop(&s->rx_fifo); in read_from_frame()
92 s->regs[SPI_RCV_DATA_REG] = (s->regs[SPI_RCV_DATA_REG] << 8) | byte; in read_from_frame()
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/qemu/
H A Dmeson_options.txt1 # These options do not correspond to a --enable/--disable-* option
3 # scripts/meson-buildoptions.py's SKIP_OPTIONS constant too.
9 option('qemu_firmwarepath', type : 'array', value : ['share/qemu-firmware'],
12 description: 'use specified string as sub-version of the package')
25 …description: 'set block driver read-write whitelist (by default affects only QEMU, not tools like …
27 …description: 'set block driver read-only whitelist (by default affects only QEMU, not tools like q…
28 option('interp_prefix', type : 'string', value : '/usr/gnemul/qemu-%M',
33 description: 'fuzzing engine library for OSS-Fuzz')
40 # Everything else can be set via --enable/--disable-* option
42 # here make sure to run "make update-buildoptions".
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/qemu/hw/audio/
H A Dasc.c7 * Copyright (c) 2012-2018 Laurent Vivier <laurent@vivier.eu>
8 * Copyright (c) 2022 Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
10 * SPDX-License-Identifier: GPL-2.0-or-later
20 #include "hw/qdev-properties.h"
42 * 7=processing time exceeded
45 * bit 1="non-ROM companding",
53 * bits 0-3 wavetables 0-3 start
55 * bits 2-4 = 3 bit internal ASC volume,
56 * bits 5-7 = volume control sent to Sony sound chip
64 * bits 6-7 = digital test,
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/qemu/qapi/
H A Dqom.json1 # -*- Mode: Python -*-
5 # See the COPYING file in the top-level directory.
8 { 'include': 'block-core.json' }
38 # @default-value: the default value, if any (since 5.0)
46 '*default-value': 'any' } }
49 # @qom-list:
54 # @path: the path within the object model. See @qom-get for a
62 # .. qmp-example::
64 # -> { "execute": "qom-list",
66 # <- { "return": [ { "name": "type", "type": "string" },
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/qemu/tests/qtest/libqos/
H A Dahci.c29 #include "pci-pc.h"
31 #include "qemu/host-utils.h"
107 g_assert(ahci->parent); in ahci_alloc()
108 return qmalloc(ahci->parent, bytes); in ahci_alloc()
114 g_assert(ahci->parent); in ahci_free()
115 qfree(ahci->parent, addr); in ahci_free()
156 QPCIBus *pcibus = dev ? dev->bus : NULL; in free_ahci_device()
163 /* Free all memory in-use by the AHCI device. */
169 if (ahci->port[port].fb) { in ahci_clean_mem()
170 ahci_free(ahci, ahci->port[port].fb); in ahci_clean_mem()
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/qemu/target/mips/tcg/
H A Dmxu_translate.c4 * Copyright (c) 2004-2005 Jocelyn Mayer
10 * SPDX-License-Identifier: LGPL-2.1-or-later
29 * video processing applications. MXU instruction set is used in Xburst family
32 * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is
41 * XRa, XRb, XRc, XRd - MXU registers
42 * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers
44 * Non-register operands:
46 * aptn1 - 1-bit accumulate add/subtract pattern
47 * aptn2 - 2-bit accumulate add/subtract pattern
48 * eptn2 - 2-bit execute add/subtract pattern
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