Lines Matching +full:processing +full:- +full:engine
6 * SPDX-License-Identifier: GPL-2.0-or-later
11 #include "hw/qdev-properties.h"
46 uint16_t rdr_match_mask = GETFIELD(SPI_MM_RDR_MATCH_MASK, s->regs[SPI_MM_REG]); in does_rdr_match()
47 uint16_t rdr_match_val = GETFIELD(SPI_MM_RDR_MATCH_VAL, s->regs[SPI_MM_REG]); in does_rdr_match()
50 GETFIELD(PPC_BITMASK(48, 63), s->regs[SPI_RCV_DATA_REG]))) { in does_rdr_match()
61 * Offset is an index between 0 and PNV_SPI_REG_SIZE - 1 in get_from_offset()
65 byte = (s->regs[SPI_XMIT_DATA_REG] >> (56 - offset * 8)) & 0xFF; in get_from_offset()
89 } else if (!fifo8_is_empty(&s->rx_fifo)) { in read_from_frame()
90 byte = fifo8_pop(&s->rx_fifo); in read_from_frame()
92 s->regs[SPI_RCV_DATA_REG] = (s->regs[SPI_RCV_DATA_REG] << 8) | byte; in read_from_frame()
109 * Processing here must handle: in spi_response()
110 * - Which bytes in the payload we should move to the RDR in spi_response()
111 * - Explicit mode counter configuration settings in spi_response()
112 * - RDR full and RDR overrun status in spi_response()
119 rx_len = fifo8_num_used(&s->rx_fifo); in spi_response()
120 if (rx_len != (s->N1_bytes + s->N2_bytes)) { in spi_response()
123 (s->N1_bytes + s->N2_bytes), rx_len); in spi_response()
127 trace_pnv_spi_log_Ncounts(s->N1_bits, s->N1_bytes, s->N1_tx, in spi_response()
128 s->N1_rx, s->N2_bits, s->N2_bytes, s->N2_tx, s->N2_rx); in spi_response()
131 * that was shifted in but cannot be loaded into RDR. Bits 29-30 of in spi_response()
137 ecc_control = GETFIELD(SPI_CLK_CFG_ECC_CTRL, s->regs[SPI_CLK_CFG_REG]); in spi_response()
149 if (s->N1_rx != 0) { in spi_response()
151 shift_in_count = read_from_frame(s, s->N1_bytes, ecc_count, shift_in_count); in spi_response()
154 if (s->N2_rx != 0) { in spi_response()
156 if (s->N1_rx == 0) { in spi_response()
157 for (i = 0; i < s->N1_bytes; i++) { in spi_response()
158 if (!fifo8_is_empty(&s->rx_fifo)) { in spi_response()
159 fifo8_pop(&s->rx_fifo); in spi_response()
167 shift_in_count = read_from_frame(s, s->N2_bytes, ecc_count, shift_in_count); in spi_response()
169 if ((s->N1_rx + s->N2_rx) > 0) { in spi_response()
177 if (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1) { in spi_response()
182 s->status = SETFIELD(SPI_STS_RDR_OVERRUN, s->status, 1); in spi_response()
188 s->status = SETFIELD(SPI_STS_RDR_FULL, s->status, 1); in spi_response()
199 payload_len = fifo8_num_used(&s->tx_fifo); in transfer()
200 for (int offset = 0; offset < payload_len; offset += s->transfer_len) { in transfer()
202 for (int i = 0; i < s->transfer_len; i++) { in transfer()
205 } else if (!fifo8_is_empty(&s->tx_fifo)) { in transfer()
206 tx = (tx << 8) | fifo8_pop(&s->tx_fifo); in transfer()
211 rx = ssi_transfer(s->ssi_bus, tx); in transfer()
212 for (int i = 0; i < s->transfer_len; i++) { in transfer()
216 rx_byte = (rx >> (8 * (s->transfer_len - 1) - i * 8)) & 0xFF; in transfer()
217 if (!fifo8_is_full(&s->rx_fifo)) { in transfer()
218 fifo8_push(&s->rx_fifo, rx_byte); in transfer()
227 fifo8_reset(&s->tx_fifo); in transfer()
228 fifo8_reset(&s->rx_fifo); in transfer()
259 s->N1_bits = GETFIELD(SPI_CTR_CFG_N1, s->regs[SPI_CTR_CFG_REG]); in calculate_N1()
260 s->N1_bytes = (s->N1_bits + 7) / 8; in calculate_N1()
261 s->N1_tx = 0; in calculate_N1()
262 s->N1_rx = 0; in calculate_N1()
264 if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B2, s->regs[SPI_CTR_CFG_REG]) == 1) { in calculate_N1()
265 s->N1_tx = s->N1_bytes; in calculate_N1()
268 if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B3, s->regs[SPI_CTR_CFG_REG]) == 1) { in calculate_N1()
269 s->N1_rx = s->N1_bytes; in calculate_N1()
273 s->N1_bytes = PNV_SPI_OPCODE_LO_NIBBLE(opcode); in calculate_N1()
274 s->N1_bits = s->N1_bytes * 8; in calculate_N1()
279 s->N1_tx = s->N1_bytes; in calculate_N1()
280 s->N1_rx = 0; in calculate_N1()
282 if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B1, s->regs[SPI_CTR_CFG_REG]) == 1) { in calculate_N1()
287 if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B2, s->regs[SPI_CTR_CFG_REG]) == 0) { in calculate_N1()
288 s->N1_tx = 0; in calculate_N1()
291 if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B3, s->regs[SPI_CTR_CFG_REG]) == 1) { in calculate_N1()
292 s->N1_rx = s->N1_bytes; in calculate_N1()
303 uint8_t ecc_control = GETFIELD(SPI_CLK_CFG_ECC_CTRL, s->regs[SPI_CLK_CFG_REG]); in calculate_N1()
305 if (s->N1_bytes > (PNV_SPI_REG_SIZE + 1)) { in calculate_N1()
308 s->N1_bytes, s->N1_bits); in calculate_N1()
309 s->N1_bytes = PNV_SPI_REG_SIZE + 1; in calculate_N1()
310 s->N1_bits = s->N1_bytes * 8; in calculate_N1()
312 } else if (s->N1_bytes > PNV_SPI_REG_SIZE) { in calculate_N1()
314 "bytes = 0x%x, bits = 0x%x\n", s->N1_bytes, s->N1_bits); in calculate_N1()
315 s->N1_bytes = PNV_SPI_REG_SIZE; in calculate_N1()
316 s->N1_bits = s->N1_bytes * 8; in calculate_N1()
338 trace_pnv_spi_log_Ncounts(s->N1_bits, s->N1_bytes, s->N1_tx, in operation_shiftn1()
339 s->N1_rx, s->N2_bits, s->N2_bytes, s->N2_tx, s->N2_rx); in operation_shiftn1()
345 s->N2_bits = 0; in operation_shiftn1()
346 s->N2_bytes = 0; in operation_shiftn1()
347 s->N2_tx = 0; in operation_shiftn1()
348 s->N2_rx = 0; in operation_shiftn1()
360 while (n1_count < s->N1_bytes) { in operation_shiftn1()
365 if ((s->N1_tx != 0) && (n1_count < PNV_SPI_REG_SIZE)) { in operation_shiftn1()
367 if (GETFIELD(SPI_STS_TDR_FULL, s->status) == 1) { in operation_shiftn1()
377 if (!fifo8_is_full(&s->tx_fifo)) { in operation_shiftn1()
379 fifo8_push(&s->tx_fifo, n1_byte); in operation_shiftn1()
397 * - we are receiving during the N1 frame segment and the RDR in operation_shiftn1()
399 * - we are transmitting and we don't care about RDR status in operation_shiftn1()
401 * - we are receiving and the RDR is empty so we allow the operation in operation_shiftn1()
404 if ((s->N1_rx != 0) && (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1)) { in operation_shiftn1()
409 } else if (!fifo8_is_full(&s->tx_fifo)) { in operation_shiftn1()
411 fifo8_push(&s->tx_fifo, 0xff); in operation_shiftn1()
428 if (!stop && (s->N1_tx != 0) && in operation_shiftn1()
429 (GETFIELD(SPI_STS_TDR_FULL, s->status) == 1)) { in operation_shiftn1()
430 s->status = SETFIELD(SPI_STS_TDR_FULL, s->status, 0); in operation_shiftn1()
442 (GETFIELD(SPI_CTR_CFG_N2_CTRL_B0, s->regs[SPI_CTR_CFG_REG]) == 1)) { in operation_shiftn1()
446 s->status = SETFIELD(SPI_STS_TDR_UNDERRUN, s->status, 1); in operation_shiftn1()
455 trace_pnv_spi_tx_request("Shifting N1 frame", fifo8_num_used(&s->tx_fifo)); in operation_shiftn1()
458 s->N2_bits = 0; in operation_shiftn1()
459 s->N2_bytes = 0; in operation_shiftn1()
460 s->N2_tx = 0; in operation_shiftn1()
461 s->N2_rx = 0; in operation_shiftn1()
494 s->N2_bits = GETFIELD(SPI_CTR_CFG_N2, s->regs[SPI_CTR_CFG_REG]); in calculate_N2()
495 s->N2_bytes = (s->N2_bits + 7) / 8; in calculate_N2()
496 s->N2_tx = 0; in calculate_N2()
497 s->N2_rx = 0; in calculate_N2()
499 if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B2, s->regs[SPI_CTR_CFG_REG]) == 1) { in calculate_N2()
500 s->N2_tx = s->N2_bytes; in calculate_N2()
503 if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B3, s->regs[SPI_CTR_CFG_REG]) == 1) { in calculate_N2()
504 s->N2_rx = s->N2_bytes; in calculate_N2()
508 s->N2_bytes = PNV_SPI_OPCODE_LO_NIBBLE(opcode); in calculate_N2()
509 s->N2_bits = s->N2_bytes * 8; in calculate_N2()
511 s->N2_rx = s->N2_bytes; in calculate_N2()
512 s->N2_tx = 0; in calculate_N2()
514 if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B1, s->regs[SPI_CTR_CFG_REG]) == 1) { in calculate_N2()
519 if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B3, s->regs[SPI_CTR_CFG_REG]) == 0) { in calculate_N2()
520 s->N2_rx = 0; in calculate_N2()
523 if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B2, s->regs[SPI_CTR_CFG_REG]) == 1) { in calculate_N2()
524 s->N2_tx = s->N2_bytes; in calculate_N2()
536 uint8_t ecc_control = GETFIELD(SPI_CLK_CFG_ECC_CTRL, s->regs[SPI_CLK_CFG_REG]); in calculate_N2()
538 if (s->N2_bytes > (PNV_SPI_REG_SIZE + 1)) { in calculate_N2()
540 s->N2_bytes = PNV_SPI_REG_SIZE + 1; in calculate_N2()
541 s->N2_bits = s->N2_bytes * 8; in calculate_N2()
543 } else if (s->N2_bytes > PNV_SPI_REG_SIZE) { in calculate_N2()
545 s->N2_bytes = PNV_SPI_REG_SIZE; in calculate_N2()
546 s->N2_bits = s->N2_bytes * 8; in calculate_N2()
563 trace_pnv_spi_log_Ncounts(s->N1_bits, s->N1_bytes, s->N1_tx, in operation_shiftn2()
564 s->N1_rx, s->N2_bits, s->N2_bytes, s->N2_tx, s->N2_rx); in operation_shiftn2()
578 while (n2_count < s->N2_bytes) { in operation_shiftn2()
584 if ((s->N2_rx != 0) && (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1)) { in operation_shiftn2()
590 if ((s->N2_tx != 0) && ((s->N1_tx + n2_count) < PNV_SPI_REG_SIZE)) { in operation_shiftn2()
593 n2_byte = get_from_offset(s, (s->N1_tx + n2_count)); in operation_shiftn2()
594 if (!fifo8_is_full(&s->tx_fifo)) { in operation_shiftn2()
595 trace_pnv_spi_tx_append("n2_byte", n2_byte, (s->N1_tx + n2_count)); in operation_shiftn2()
596 fifo8_push(&s->tx_fifo, n2_byte); in operation_shiftn2()
601 } else if (!fifo8_is_full(&s->tx_fifo)) { in operation_shiftn2()
608 fifo8_push(&s->tx_fifo, 0xff); in operation_shiftn2()
617 trace_pnv_spi_tx_request("Shifting N2 frame", fifo8_num_used(&s->tx_fifo)); in operation_shiftn2()
624 if ((s->N2_tx != 0) && (GETFIELD(SPI_STS_TDR_FULL, s->status) == 1)) { in operation_shiftn2()
625 s->status = SETFIELD(SPI_STS_TDR_FULL, s->status, 0); in operation_shiftn2()
632 s->N2_bits = 0; in operation_shiftn2()
633 s->N2_bytes = 0; in operation_shiftn2()
634 s->N2_tx = 0; in operation_shiftn2()
635 s->N2_rx = 0; in operation_shiftn2()
636 s->N1_bits = 0; in operation_shiftn2()
637 s->N1_bytes = 0; in operation_shiftn2()
638 s->N1_tx = 0; in operation_shiftn2()
639 s->N1_rx = 0; in operation_shiftn2()
659 * Clear the sequencer FSM error bit - general_SPI_status[3] in operation_sequencer()
662 s->status = SETFIELD(SPI_STS_GEN_STATUS_B3, s->status, 0); in operation_sequencer()
667 if (GETFIELD(SPI_STS_SEQ_FSM, s->status) == SEQ_STATE_IDLE) { in operation_sequencer()
668 s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status, 0); in operation_sequencer()
674 seq_index = GETFIELD(SPI_STS_SEQ_INDEX, s->status); in operation_sequencer()
680 opcode = s->seq_op[seq_index]; in operation_sequencer()
682 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_DECODE); in operation_sequencer()
695 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
700 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_IDLE); in operation_sequencer()
701 s->loop_counter_1 = 0; in operation_sequencer()
702 s->loop_counter_2 = 0; in operation_sequencer()
703 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_IDLE); in operation_sequencer()
707 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
711 * connection at position 0. De-selecting a responder is fine in operation_sequencer()
715 s->responder_select = PNV_SPI_OPCODE_LO_NIBBLE(opcode); in operation_sequencer()
716 if (s->responder_select == 0) { in operation_sequencer()
718 qemu_set_irq(s->cs_line[0], 1); in operation_sequencer()
720 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_DONE); in operation_sequencer()
721 } else if (s->responder_select != 1) { in operation_sequencer()
723 "not supported, select = 0x%x\n", s->responder_select); in operation_sequencer()
725 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_IDLE); in operation_sequencer()
732 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_START); in operation_sequencer()
734 qemu_set_irq(s->cs_line[0], 0); in operation_sequencer()
743 s->shift_n1_done = false; in operation_sequencer()
745 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, in operation_sequencer()
751 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
757 * - processed a responder deselect (DONE) in operation_sequencer()
758 * - processed a stop opcode (IDLE) in operation_sequencer()
759 * - encountered an error (IDLE) in operation_sequencer()
761 if ((GETFIELD(SPI_STS_SHIFTER_FSM, s->status) == FSM_IDLE) || in operation_sequencer()
762 (GETFIELD(SPI_STS_SHIFTER_FSM, s->status) == FSM_DONE)) { in operation_sequencer()
765 SPI_STS_SHIFTER_FSM, s->status)); in operation_sequencer()
770 s->status = SETFIELD(SPI_STS_GEN_STATUS_B3, s->status, 1); in operation_sequencer()
785 PNV_SPI_MASKED_OPCODE(s->seq_op[(seq_index + 1)]) == in operation_sequencer()
789 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_SHIFT_N1); in operation_sequencer()
803 if (GETFIELD(SPI_STS_TDR_UNDERRUN, s->status)) { in operation_sequencer()
804 s->shift_n1_done = true; in operation_sequencer()
805 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, in operation_sequencer()
813 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_WAIT); in operation_sequencer()
817 s->shift_n1_done = true; in operation_sequencer()
819 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, in operation_sequencer()
826 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
828 if (!s->shift_n1_done) { in operation_sequencer()
831 GETFIELD(SPI_STS_SHIFTER_FSM, s->status)); in operation_sequencer()
837 s->status = SETFIELD(SPI_STS_GEN_STATUS_B3, s->status, 1); in operation_sequencer()
842 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_SHIFT_N2); in operation_sequencer()
849 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_WAIT); in operation_sequencer()
853 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, in operation_sequencer()
860 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
871 if (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1) { in operation_sequencer()
876 s->fail_count = 0; in operation_sequencer()
879 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, in operation_sequencer()
883 s->fail_count++; in operation_sequencer()
890 if (s->fail_count >= RDR_MATCH_FAILURE_LIMIT) { in operation_sequencer()
902 s->status = SETFIELD(SPI_STS_RDR_FULL, s->status, 0); in operation_sequencer()
907 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_WAIT); in operation_sequencer()
912 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
915 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_INDEX_INCREMENT); in operation_sequencer()
919 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
925 * no-op in operation_sequencer()
927 if (s->loop_counter_1 != in operation_sequencer()
928 GETFIELD(SPI_CTR_CFG_CMP1, s->regs[SPI_CTR_CFG_REG])) { in operation_sequencer()
935 s->loop_counter_1++; in operation_sequencer()
939 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, in operation_sequencer()
945 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
948 s->regs[SPI_CTR_CFG_REG]); in operation_sequencer()
953 * no-op in operation_sequencer()
955 if (s->loop_counter_2 != condition2) { in operation_sequencer()
962 s->loop_counter_2++; in operation_sequencer()
966 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, in operation_sequencer()
972 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); in operation_sequencer()
975 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_INDEX_INCREMENT); in operation_sequencer()
979 * If we used all 8 opcodes without seeing a 00 - STOP in the sequence in operation_sequencer()
985 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_IDLE); in operation_sequencer()
987 s->loop_counter_1 = 0; in operation_sequencer()
988 s->loop_counter_2 = 0; in operation_sequencer()
989 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_IDLE); in operation_sequencer()
998 s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status, seq_index); in operation_sequencer()
1002 * The SPIC engine and its internal sequencer can be interrupted and reset by
1008 * not reset. The engine registers are not reset.
1009 * The SPIC engine reset does not have any affect on the attached devices.
1010 * Reset handling of any attached devices is beyond the scope of the engine.
1020 ssi_dev = ssi_get_cs(s->ssi_bus, 0); in do_reset()
1027 s->N2_bits = 0; in do_reset()
1028 s->N2_bytes = 0; in do_reset()
1029 s->N2_tx = 0; in do_reset()
1030 s->N2_rx = 0; in do_reset()
1031 s->N1_bits = 0; in do_reset()
1032 s->N1_bytes = 0; in do_reset()
1033 s->N1_tx = 0; in do_reset()
1034 s->N1_rx = 0; in do_reset()
1035 s->loop_counter_1 = 0; in do_reset()
1036 s->loop_counter_2 = 0; in do_reset()
1038 qemu_set_irq(s->cs_line[0], 1); in do_reset()
1054 val = s->regs[reg]; in pnv_spi_xscom_read()
1057 val = s->regs[reg]; in pnv_spi_xscom_read()
1059 s->status = SETFIELD(SPI_STS_RDR_FULL, s->status, 0); in pnv_spi_xscom_read()
1060 if (GETFIELD(SPI_STS_SHIFTER_FSM, s->status) == FSM_WAIT) { in pnv_spi_xscom_read()
1068 val = (val << 8) | s->seq_op[i]; in pnv_spi_xscom_read()
1072 val = s->status; in pnv_spi_xscom_read()
1097 s->regs[reg] = val; in pnv_spi_xscom_write()
1104 if ((GETFIELD(SPI_CLK_CFG_RST_CTRL, s->regs[SPI_CLK_CFG_REG]) == 0x5) in pnv_spi_xscom_write()
1107 s->regs[reg] = SPI_CLK_CFG_HARD_RST; in pnv_spi_xscom_write()
1109 s->regs[reg] = val; in pnv_spi_xscom_write()
1121 s->regs[reg] = val; in pnv_spi_xscom_write()
1123 s->status = SETFIELD(SPI_STS_TDR_FULL, s->status, 1); in pnv_spi_xscom_write()
1124 s->status = SETFIELD(SPI_STS_TDR_UNDERRUN, s->status, 0); in pnv_spi_xscom_write()
1130 s->seq_op[i] = (val >> (56 - i * 8)) & 0xFF; in pnv_spi_xscom_write()
1135 s->status = SETFIELD(SPI_STS_RDR_OVERRUN, s->status, in pnv_spi_xscom_write()
1137 s->status = SETFIELD(SPI_STS_TDR_OVERRUN, s->status, in pnv_spi_xscom_write()
1158 DEFINE_PROP_UINT32("chip-id", PnvSpi, chip_id, 0),
1166 s->chip_id, s->spic_num); in pnv_spi_realize()
1167 s->ssi_bus = ssi_create_bus(dev, name); in pnv_spi_realize()
1168 s->cs_line = g_new0(qemu_irq, 1); in pnv_spi_realize()
1169 qdev_init_gpio_out_named(DEVICE(s), s->cs_line, "cs", 1); in pnv_spi_realize()
1171 fifo8_create(&s->tx_fifo, PNV_SPI_FIFO_SIZE); in pnv_spi_realize()
1172 fifo8_create(&s->rx_fifo, PNV_SPI_FIFO_SIZE); in pnv_spi_realize()
1175 pnv_xscom_region_init(&s->xscom_spic_regs, OBJECT(s), &pnv_spi_xscom_ops, in pnv_spi_realize()
1176 s, "xscom-spi", PNV10_XSCOM_PIB_SPIC_SIZE); in pnv_spi_realize()
1185 const char compat[] = "ibm,power10-spi"; in pnv_spi_dt_xscom()
1187 s->spic_num * PNV10_XSCOM_PIB_SPIC_SIZE; in pnv_spi_dt_xscom()
1198 _FDT((fdt_setprop_cell(fdt, s_offset, "spic_num#", s->spic_num))); in pnv_spi_dt_xscom()
1207 xscomc->dt_xscom = pnv_spi_dt_xscom; in pnv_spi_class_init()
1209 dc->desc = "PowerNV SPI"; in pnv_spi_class_init()
1210 dc->realize = pnv_spi_realize; in pnv_spi_class_init()