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/linux/Documentation/devicetree/bindings/pci/
H A Dbrcm,iproc-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - enum:
22 - brcm,iproc-pcie
23 # for the second generation of PAXB-based controllers, used in
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H A Dmediatek-pcie-gen3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jianjun Wang <jianjun.wang@mediatek.com>
16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
19 +-----+
21 +-----+
24 port->irq
26 +-+-+-+-+-+-+-+-+
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/linux/arch/powerpc/sysdev/
H A Dmsi_bitmap.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2006-2008, Michael Ellerman, IBM Corporation.
18 int offset, order = get_count_order(num); in msi_bitmap_alloc_hwirqs() local
20 spin_lock_irqsave(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs()
22 offset = bitmap_find_next_zero_area(bmp->bitmap, bmp->irq_count, 0, in msi_bitmap_alloc_hwirqs()
23 num, (1 << order) - 1); in msi_bitmap_alloc_hwirqs()
24 if (offset > bmp->irq_count) in msi_bitmap_alloc_hwirqs()
27 bitmap_set(bmp->bitmap, offset, num); in msi_bitmap_alloc_hwirqs()
28 spin_unlock_irqrestore(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs()
30 pr_debug("msi_bitmap: allocated 0x%x at offset 0x%x\n", num, offset); in msi_bitmap_alloc_hwirqs()
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
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H A Dbrcm,bcm2712-msix.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2712-msix.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom bcm2712 MSI-X Interrupt Peripheral support
10 - Stanimir Varbanov <svarbanov@suse.de>
15 external MSI-X controller for PCIe root complex.
18 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
22 const: brcm,bcm2712-mip
26 - description: Base register address
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H A Dfsl,mpic-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mpic-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale MSI interrupt controller
10 The Freescale hypervisor and msi-address-64
11 -------------------------------------------
14 Freescale MSI driver calculates the address of MSIIR (in the MSI register
15 block) and sets that address as the MSI message address.
39 this. The address specified in the msi-address-64 property is the PCI
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/linux/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
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/linux/Documentation/PCI/endpoint/
H A Dpci-ntb-function.rst1 .. SPDX-License-Identifier: GPL-2.0
9 PCI Non-Transparent Bridges (NTB) allow two host systems to communicate
26 .. code-block:: text
28 +-------------+ +-------------+
32 +------^------+ +------^------+
35 +---------|-------------------------------------------------|---------+
36 | +------v------+ +------v------+ |
40 | | <-----------------------------------> | |
45 | +-------------+ +-------------+ |
46 +---------------------------------------------------------------------+
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/linux/drivers/xen/xen-pciback/
H A Dconf_space_capability.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Backend - Handles the virtual fields found on the capability lists
26 .offset = PCI_CAP_LIST_ID,
36 list_add_tail(&cap->cap_list, &capabilities); in register_capability()
46 cap_offset = pci_find_capability(dev, cap->capability); in xen_pcibk_config_capability_add_fields()
48 dev_dbg(&dev->dev, "Found capability 0x%x at 0x%x\n", in xen_pcibk_config_capability_add_fields()
49 cap->capability, cap_offset); in xen_pcibk_config_capability_add_fields()
57 cap->fields, in xen_pcibk_config_capability_add_fields()
68 static int vpd_address_write(struct pci_dev *dev, int offset, u16 value, in vpd_address_write() argument
75 return pci_write_config_word(dev, offset, value); in vpd_address_write()
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/linux/drivers/irqchip/
H A Dirq-bcm2712-mip.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/msi.h>
14 #include <linux/irqchip/irq-msi-lib.h>
30 * struct mip_priv - MSI-X interrupt controller data
33 * @msg_addr: PCIe MSI-X address
34 * @msi_base: MSI base
36 * @msi_offset: MSI offset
57 msg->address_hi = upper_32_bits(mip->msg_addr); in mip_compose_msi_msg()
58 msg->address_lo = lower_32_bits(mip->msg_addr); in mip_compose_msi_msg()
59 msg->data = d->hwirq; in mip_compose_msi_msg()
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/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #include <linux/msi.h>
29 #define PAB_REG_ADDR(offset, win) \ argument
30 (offset + (win * PAB_REG_BLOCK_SIZE))
31 #define PAB_EXT_REG_ADDR(offset, win) \ argument
32 (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
100 /* starting offset of INTX bits in status register */
103 /* supported number of MSI interrupts */
106 /* MSI registers */
136 struct mobiveil_msi { /* MSI information */
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/linux/include/linux/
H A Dpci-epc.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/pci-epf.h>
17 UNKNOWN_INTERFACE = -1,
36 * struct pci_epc_map - information about EPC memory for mapping a RC PCI
65 * struct pci_epc_ops - set of function pointers for performing EPC operations
69 * @align_addr: operation to get the mapping address, mapping size and offset
74 * @set_msi: ops to set the requested number of MSI interrupts in the MSI
76 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
77 * the MSI capability register
78 * @set_msix: ops to set the requested number of MSI-X interrupts in the
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/linux/Documentation/misc-devices/
H A Dspear-pcie-gadget.rst1 .. SPDX-License-Identifier: GPL-2.0
37 -----------------------
42 no_of_msi zero if MSI is not enabled by host. A positive value is the
43 number of MSI vector granted.
48 bar0_rw_offset returns offset of bar0 for which bar0_data will return value.
53 ------------------------
58 INTA, MSI or NO_INT). Select MSI only when you have programmed
60 no_of_msi number of MSI vector needed.
61 inta write 1 to assert INTA and 0 to de-assert.
62 send_msi write MSI vector to be sent.
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/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_lib.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2024 Intel Corporation. */
9 * ixgbe_cache_ring_dcb_sriov - Descriptor ring to register mapping for SR-IOV
12 * Cache the descriptor ring offsets for SR-IOV to the assigned rings. It
20 struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_cache_ring_dcb_sriov()
22 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; in ixgbe_cache_ring_dcb_sriov()
25 u8 tcs = adapter->hw_tcs; in ixgbe_cache_ring_dcb_sriov()
32 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) in ixgbe_cache_ring_dcb_sriov()
35 /* start at VMDq register offset for SR-IOV enabled setups */ in ixgbe_cache_ring_dcb_sriov()
36 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
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/linux/drivers/pci/controller/
H A Dpci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
25 #include <linux/irqchip/irq-msi-lib.h>
30 #include <linux/msi.h>
257 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
345 struct tegra_msi msi; member
357 static inline struct tegra_pcie *msi_to_pcie(struct tegra_msi *msi) in msi_to_pcie() argument
359 return container_of(msi, struct tegra_pcie, msi); in msi_to_pcie()
377 unsigned long offset) in afi_writel() argument
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H A Dpcie-rockchip-ep.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
18 #include <linux/pci-epc.h>
20 #include <linux/pci-epf.h>
24 #include "pcie-rockchip.h"
27 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
33 * @irq_phys_addr: base address on the AXI bus where the MSI/INTX IRQ
36 * the sending of a memory write (MSI) / normal message (INTX
38 * @irq_pci_addr: used to save the current mapping of the MSI/INTX IRQ
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H A Dvmd.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/irqchip/irq-msi-lib.h>
13 #include <linux/msi.h>
15 #include <linux/pci-acpi.h>
16 #include <linux/pci-ecam.h>
56 * vendor-specific capability space
61 * Device may use MSI-X vector 0 for software triggering and will not
62 * be used for MSI remapping
67 * Device can bypass remapping MSI-X transactions into its MSI-X table,
68 * avoiding the requirement of a VMD MSI domain for child device
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/linux/drivers/bluetooth/
H A Dbtintel_pcie.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
58 /* Registers for MSI-X */
107 * Host-Device interface is active
108 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD)
109 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD)
147 /* Minimum and Maximum number of MSI-X Vector
194 * All members are write-only for host and read-only for device.
219 * @tr_msi_vec: Transfer Ring MSI-X Vector
220 * @cr_msi_vec: Completion Ring MSI-X Vector
436 * @irq_lock: spinlock for MSI-X
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/linux/drivers/net/wireless/ath/ath11k/
H A Dpci.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
8 #include <linux/msi.h>
49 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); in ath11k_pci_bus_wake_up()
56 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); in ath11k_pci_bus_release()
59 static u32 ath11k_pci_get_window_start(struct ath11k_base *ab, u32 offset) in ath11k_pci_get_window_start() argument
61 if (!ab->hw_params.static_window_map) in ath11k_pci_get_window_start()
64 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK) in ath11k_pci_get_window_start()
65 /* if offset lies within DP register range, use 3rd window */ in ath11k_pci_get_window_start()
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H A Dpcic.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
15 "mhi-er0",
16 "mhi-er1",
29 "host2wbm-desc-feed",
30 "host2reo-re-injection",
31 "host2reo-command",
32 "host2rxdma-monitor-ring3",
33 "host2rxdma-monitor-ring2",
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/linux/Documentation/devicetree/bindings/powerpc/4xx/
H A Dhsta.txt10 Currently only the MSI support is used by Linux using the following
14 - compatible : "ibm,476gtr-hsta-msi", "ibm,hsta-msi"
15 - reg : register mapping for the HSTA MSI space
16 - interrupts : ordered interrupt mapping for each MSI in the register
18 register offset of 0x00, the second to 0x10, etc.
/linux/arch/arm64/boot/dts/apm/
H A Dapm-shadowcat.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
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/linux/drivers/pci/controller/plda/
H A Dpcie-microchip-host.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
18 #include <linux/msi.h>
21 #include <linux/pci-ecam.h>
26 #include "../pci-host-common.h"
27 #include "pcie-plda.h"
88 /* PCIe Config space MSI capability structure */
136 .offset = PCIE_EVENT_INT, \
143 .offset = SEC_ERROR_INT, \
150 .offset = DED_ERROR_INT, \
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/linux/drivers/iommu/iommufd/
H A Ddriver.c1 // SPDX-License-Identifier: GPL-2.0-only
6 /* Driver should use a per-structure helper in include/linux/iommufd.h */
12 return -EINVAL; in _iommufd_object_depend()
14 if (obj_dependent->type != obj_depended->type) in _iommufd_object_depend()
15 return -EINVAL; in _iommufd_object_depend()
17 refcount_inc(&obj_depended->users); in _iommufd_object_depend()
22 /* Driver should use a per-structure helper in include/linux/iommufd.h */
27 obj_dependent->type != obj_depended->type)) in _iommufd_object_undepend()
30 refcount_dec(&obj_depended->users); in _iommufd_object_undepend()
35 * Allocate an @offset to return to user space to use for an mmap() syscall
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/linux/Documentation/ABI/testing/
H A Ddebugfs-msi-wmi-platform1 What: /sys/kernel/debug/msi-wmi-platform-<wmi_device_name>/*
9 at file offset 0. Partial writes or writes at a different offset are not
14 See Documentation/wmi/devices/msi-wmi-platform.rst for details.

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