1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip AXI PCIe Bridge host controller driver 4 * 5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved. 6 * 7 * Author: Daire McNamara <daire.mcnamara@microchip.com> 8 */ 9 10 #include <linux/align.h> 11 #include <linux/bits.h> 12 #include <linux/bitfield.h> 13 #include <linux/clk.h> 14 #include <linux/irqchip/chained_irq.h> 15 #include <linux/irqdomain.h> 16 #include <linux/log2.h> 17 #include <linux/module.h> 18 #include <linux/msi.h> 19 #include <linux/of_address.h> 20 #include <linux/of_pci.h> 21 #include <linux/pci-ecam.h> 22 #include <linux/platform_device.h> 23 #include <linux/wordpart.h> 24 25 #include "../../pci.h" 26 #include "../pci-host-common.h" 27 #include "pcie-plda.h" 28 29 #define MC_MAX_NUM_INBOUND_WINDOWS 8 30 #define MPFS_NC_BOUNCE_ADDR 0x80000000 31 32 /* PCIe Bridge Phy and Controller Phy offsets */ 33 #define MC_PCIE1_BRIDGE_ADDR 0x00008000u 34 #define MC_PCIE1_CTRL_ADDR 0x0000a000u 35 36 /* PCIe Controller Phy Regs */ 37 #define SEC_ERROR_EVENT_CNT 0x20 38 #define DED_ERROR_EVENT_CNT 0x24 39 #define SEC_ERROR_INT 0x28 40 #define SEC_ERROR_INT_TX_RAM_SEC_ERR_INT GENMASK(3, 0) 41 #define SEC_ERROR_INT_RX_RAM_SEC_ERR_INT GENMASK(7, 4) 42 #define SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT GENMASK(11, 8) 43 #define SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT GENMASK(15, 12) 44 #define SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT GENMASK(15, 0) 45 #define NUM_SEC_ERROR_INTS (4) 46 #define SEC_ERROR_INT_MASK 0x2c 47 #define DED_ERROR_INT 0x30 48 #define DED_ERROR_INT_TX_RAM_DED_ERR_INT GENMASK(3, 0) 49 #define DED_ERROR_INT_RX_RAM_DED_ERR_INT GENMASK(7, 4) 50 #define DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT GENMASK(11, 8) 51 #define DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT GENMASK(15, 12) 52 #define DED_ERROR_INT_ALL_RAM_DED_ERR_INT GENMASK(15, 0) 53 #define NUM_DED_ERROR_INTS (4) 54 #define DED_ERROR_INT_MASK 0x34 55 #define ECC_CONTROL 0x38 56 #define ECC_CONTROL_TX_RAM_INJ_ERROR_0 BIT(0) 57 #define ECC_CONTROL_TX_RAM_INJ_ERROR_1 BIT(1) 58 #define ECC_CONTROL_TX_RAM_INJ_ERROR_2 BIT(2) 59 #define ECC_CONTROL_TX_RAM_INJ_ERROR_3 BIT(3) 60 #define ECC_CONTROL_RX_RAM_INJ_ERROR_0 BIT(4) 61 #define ECC_CONTROL_RX_RAM_INJ_ERROR_1 BIT(5) 62 #define ECC_CONTROL_RX_RAM_INJ_ERROR_2 BIT(6) 63 #define ECC_CONTROL_RX_RAM_INJ_ERROR_3 BIT(7) 64 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0 BIT(8) 65 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1 BIT(9) 66 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2 BIT(10) 67 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3 BIT(11) 68 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0 BIT(12) 69 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1 BIT(13) 70 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2 BIT(14) 71 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3 BIT(15) 72 #define ECC_CONTROL_TX_RAM_ECC_BYPASS BIT(24) 73 #define ECC_CONTROL_RX_RAM_ECC_BYPASS BIT(25) 74 #define ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS BIT(26) 75 #define ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS BIT(27) 76 #define PCIE_EVENT_INT 0x14c 77 #define PCIE_EVENT_INT_L2_EXIT_INT BIT(0) 78 #define PCIE_EVENT_INT_HOTRST_EXIT_INT BIT(1) 79 #define PCIE_EVENT_INT_DLUP_EXIT_INT BIT(2) 80 #define PCIE_EVENT_INT_MASK GENMASK(2, 0) 81 #define PCIE_EVENT_INT_L2_EXIT_INT_MASK BIT(16) 82 #define PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK BIT(17) 83 #define PCIE_EVENT_INT_DLUP_EXIT_INT_MASK BIT(18) 84 #define PCIE_EVENT_INT_ENB_MASK GENMASK(18, 16) 85 #define PCIE_EVENT_INT_ENB_SHIFT 16 86 #define NUM_PCIE_EVENTS (3) 87 88 /* PCIe Config space MSI capability structure */ 89 #define MC_MSI_CAP_CTRL_OFFSET 0xe0u 90 91 /* Events */ 92 #define EVENT_PCIE_L2_EXIT 0 93 #define EVENT_PCIE_HOTRST_EXIT 1 94 #define EVENT_PCIE_DLUP_EXIT 2 95 #define EVENT_SEC_TX_RAM_SEC_ERR 3 96 #define EVENT_SEC_RX_RAM_SEC_ERR 4 97 #define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 5 98 #define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 6 99 #define EVENT_DED_TX_RAM_DED_ERR 7 100 #define EVENT_DED_RX_RAM_DED_ERR 8 101 #define EVENT_DED_PCIE2AXI_RAM_DED_ERR 9 102 #define EVENT_DED_AXI2PCIE_RAM_DED_ERR 10 103 #define EVENT_LOCAL_DMA_END_ENGINE_0 11 104 #define EVENT_LOCAL_DMA_END_ENGINE_1 12 105 #define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13 106 #define EVENT_LOCAL_DMA_ERROR_ENGINE_1 14 107 #define NUM_MC_EVENTS 15 108 #define EVENT_LOCAL_A_ATR_EVT_POST_ERR (NUM_MC_EVENTS + PLDA_AXI_POST_ERR) 109 #define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + PLDA_AXI_FETCH_ERR) 110 #define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + PLDA_AXI_DISCARD_ERR) 111 #define EVENT_LOCAL_A_ATR_EVT_DOORBELL (NUM_MC_EVENTS + PLDA_AXI_DOORBELL) 112 #define EVENT_LOCAL_P_ATR_EVT_POST_ERR (NUM_MC_EVENTS + PLDA_PCIE_POST_ERR) 113 #define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR (NUM_MC_EVENTS + PLDA_PCIE_FETCH_ERR) 114 #define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR (NUM_MC_EVENTS + PLDA_PCIE_DISCARD_ERR) 115 #define EVENT_LOCAL_P_ATR_EVT_DOORBELL (NUM_MC_EVENTS + PLDA_PCIE_DOORBELL) 116 #define EVENT_LOCAL_PM_MSI_INT_INTX (NUM_MC_EVENTS + PLDA_INTX) 117 #define EVENT_LOCAL_PM_MSI_INT_MSI (NUM_MC_EVENTS + PLDA_MSI) 118 #define EVENT_LOCAL_PM_MSI_INT_AER_EVT (NUM_MC_EVENTS + PLDA_AER_EVENT) 119 #define EVENT_LOCAL_PM_MSI_INT_EVENTS (NUM_MC_EVENTS + PLDA_MISC_EVENTS) 120 #define EVENT_LOCAL_PM_MSI_INT_SYS_ERR (NUM_MC_EVENTS + PLDA_SYS_ERR) 121 #define NUM_EVENTS (NUM_MC_EVENTS + PLDA_INT_EVENT_NUM) 122 123 #define PCIE_EVENT_CAUSE(x, s) \ 124 [EVENT_PCIE_ ## x] = { __stringify(x), s } 125 126 #define SEC_ERROR_CAUSE(x, s) \ 127 [EVENT_SEC_ ## x] = { __stringify(x), s } 128 129 #define DED_ERROR_CAUSE(x, s) \ 130 [EVENT_DED_ ## x] = { __stringify(x), s } 131 132 #define LOCAL_EVENT_CAUSE(x, s) \ 133 [EVENT_LOCAL_ ## x] = { __stringify(x), s } 134 135 #define PCIE_EVENT(x) \ 136 .offset = PCIE_EVENT_INT, \ 137 .mask_offset = PCIE_EVENT_INT, \ 138 .mask_high = 1, \ 139 .mask = PCIE_EVENT_INT_ ## x ## _INT, \ 140 .enb_mask = PCIE_EVENT_INT_ENB_MASK 141 142 #define SEC_EVENT(x) \ 143 .offset = SEC_ERROR_INT, \ 144 .mask_offset = SEC_ERROR_INT_MASK, \ 145 .mask = SEC_ERROR_INT_ ## x ## _INT, \ 146 .mask_high = 1, \ 147 .enb_mask = 0 148 149 #define DED_EVENT(x) \ 150 .offset = DED_ERROR_INT, \ 151 .mask_offset = DED_ERROR_INT_MASK, \ 152 .mask_high = 1, \ 153 .mask = DED_ERROR_INT_ ## x ## _INT, \ 154 .enb_mask = 0 155 156 #define LOCAL_EVENT(x) \ 157 .offset = ISTATUS_LOCAL, \ 158 .mask_offset = IMASK_LOCAL, \ 159 .mask_high = 0, \ 160 .mask = x ## _MASK, \ 161 .enb_mask = 0 162 163 #define PCIE_EVENT_TO_EVENT_MAP(x) \ 164 { PCIE_EVENT_INT_ ## x ## _INT, EVENT_PCIE_ ## x } 165 166 #define SEC_ERROR_TO_EVENT_MAP(x) \ 167 { SEC_ERROR_INT_ ## x ## _INT, EVENT_SEC_ ## x } 168 169 #define DED_ERROR_TO_EVENT_MAP(x) \ 170 { DED_ERROR_INT_ ## x ## _INT, EVENT_DED_ ## x } 171 172 #define LOCAL_STATUS_TO_EVENT_MAP(x) \ 173 { x ## _MASK, EVENT_LOCAL_ ## x } 174 175 struct event_map { 176 u32 reg_mask; 177 u32 event_bit; 178 }; 179 180 181 struct mc_pcie { 182 struct plda_pcie_rp plda; 183 void __iomem *bridge_base_addr; 184 void __iomem *ctrl_base_addr; 185 }; 186 187 struct cause { 188 const char *sym; 189 const char *str; 190 }; 191 192 static const struct cause event_cause[NUM_EVENTS] = { 193 PCIE_EVENT_CAUSE(L2_EXIT, "L2 exit event"), 194 PCIE_EVENT_CAUSE(HOTRST_EXIT, "Hot reset exit event"), 195 PCIE_EVENT_CAUSE(DLUP_EXIT, "DLUP exit event"), 196 SEC_ERROR_CAUSE(TX_RAM_SEC_ERR, "sec error in tx buffer"), 197 SEC_ERROR_CAUSE(RX_RAM_SEC_ERR, "sec error in rx buffer"), 198 SEC_ERROR_CAUSE(PCIE2AXI_RAM_SEC_ERR, "sec error in pcie2axi buffer"), 199 SEC_ERROR_CAUSE(AXI2PCIE_RAM_SEC_ERR, "sec error in axi2pcie buffer"), 200 DED_ERROR_CAUSE(TX_RAM_DED_ERR, "ded error in tx buffer"), 201 DED_ERROR_CAUSE(RX_RAM_DED_ERR, "ded error in rx buffer"), 202 DED_ERROR_CAUSE(PCIE2AXI_RAM_DED_ERR, "ded error in pcie2axi buffer"), 203 DED_ERROR_CAUSE(AXI2PCIE_RAM_DED_ERR, "ded error in axi2pcie buffer"), 204 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_0, "dma engine 0 error"), 205 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_1, "dma engine 1 error"), 206 LOCAL_EVENT_CAUSE(A_ATR_EVT_POST_ERR, "axi write request error"), 207 LOCAL_EVENT_CAUSE(A_ATR_EVT_FETCH_ERR, "axi read request error"), 208 LOCAL_EVENT_CAUSE(A_ATR_EVT_DISCARD_ERR, "axi read timeout"), 209 LOCAL_EVENT_CAUSE(P_ATR_EVT_POST_ERR, "pcie write request error"), 210 LOCAL_EVENT_CAUSE(P_ATR_EVT_FETCH_ERR, "pcie read request error"), 211 LOCAL_EVENT_CAUSE(P_ATR_EVT_DISCARD_ERR, "pcie read timeout"), 212 LOCAL_EVENT_CAUSE(PM_MSI_INT_AER_EVT, "aer event"), 213 LOCAL_EVENT_CAUSE(PM_MSI_INT_EVENTS, "pm/ltr/hotplug event"), 214 LOCAL_EVENT_CAUSE(PM_MSI_INT_SYS_ERR, "system error"), 215 }; 216 217 static struct event_map pcie_event_to_event[] = { 218 PCIE_EVENT_TO_EVENT_MAP(L2_EXIT), 219 PCIE_EVENT_TO_EVENT_MAP(HOTRST_EXIT), 220 PCIE_EVENT_TO_EVENT_MAP(DLUP_EXIT), 221 }; 222 223 static struct event_map sec_error_to_event[] = { 224 SEC_ERROR_TO_EVENT_MAP(TX_RAM_SEC_ERR), 225 SEC_ERROR_TO_EVENT_MAP(RX_RAM_SEC_ERR), 226 SEC_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_SEC_ERR), 227 SEC_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_SEC_ERR), 228 }; 229 230 static struct event_map ded_error_to_event[] = { 231 DED_ERROR_TO_EVENT_MAP(TX_RAM_DED_ERR), 232 DED_ERROR_TO_EVENT_MAP(RX_RAM_DED_ERR), 233 DED_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_DED_ERR), 234 DED_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_DED_ERR), 235 }; 236 237 static struct event_map local_status_to_event[] = { 238 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_0), 239 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_1), 240 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_0), 241 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_1), 242 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_POST_ERR), 243 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_FETCH_ERR), 244 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DISCARD_ERR), 245 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DOORBELL), 246 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_POST_ERR), 247 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_FETCH_ERR), 248 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DISCARD_ERR), 249 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DOORBELL), 250 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_INTX), 251 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_MSI), 252 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_AER_EVT), 253 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_EVENTS), 254 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_SYS_ERR), 255 }; 256 257 static struct { 258 u32 offset; 259 u32 mask; 260 u32 shift; 261 u32 enb_mask; 262 u32 mask_high; 263 u32 mask_offset; 264 } event_descs[] = { 265 { PCIE_EVENT(L2_EXIT) }, 266 { PCIE_EVENT(HOTRST_EXIT) }, 267 { PCIE_EVENT(DLUP_EXIT) }, 268 { SEC_EVENT(TX_RAM_SEC_ERR) }, 269 { SEC_EVENT(RX_RAM_SEC_ERR) }, 270 { SEC_EVENT(PCIE2AXI_RAM_SEC_ERR) }, 271 { SEC_EVENT(AXI2PCIE_RAM_SEC_ERR) }, 272 { DED_EVENT(TX_RAM_DED_ERR) }, 273 { DED_EVENT(RX_RAM_DED_ERR) }, 274 { DED_EVENT(PCIE2AXI_RAM_DED_ERR) }, 275 { DED_EVENT(AXI2PCIE_RAM_DED_ERR) }, 276 { LOCAL_EVENT(DMA_END_ENGINE_0) }, 277 { LOCAL_EVENT(DMA_END_ENGINE_1) }, 278 { LOCAL_EVENT(DMA_ERROR_ENGINE_0) }, 279 { LOCAL_EVENT(DMA_ERROR_ENGINE_1) }, 280 { LOCAL_EVENT(A_ATR_EVT_POST_ERR) }, 281 { LOCAL_EVENT(A_ATR_EVT_FETCH_ERR) }, 282 { LOCAL_EVENT(A_ATR_EVT_DISCARD_ERR) }, 283 { LOCAL_EVENT(A_ATR_EVT_DOORBELL) }, 284 { LOCAL_EVENT(P_ATR_EVT_POST_ERR) }, 285 { LOCAL_EVENT(P_ATR_EVT_FETCH_ERR) }, 286 { LOCAL_EVENT(P_ATR_EVT_DISCARD_ERR) }, 287 { LOCAL_EVENT(P_ATR_EVT_DOORBELL) }, 288 { LOCAL_EVENT(PM_MSI_INT_INTX) }, 289 { LOCAL_EVENT(PM_MSI_INT_MSI) }, 290 { LOCAL_EVENT(PM_MSI_INT_AER_EVT) }, 291 { LOCAL_EVENT(PM_MSI_INT_EVENTS) }, 292 { LOCAL_EVENT(PM_MSI_INT_SYS_ERR) }, 293 }; 294 295 static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" }; 296 297 static struct mc_pcie *port; 298 299 static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam) 300 { 301 struct plda_msi *msi = &port->plda.msi; 302 u16 reg; 303 u8 queue_size; 304 305 /* Fixup MSI enable flag */ 306 reg = readw_relaxed(ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS); 307 reg |= PCI_MSI_FLAGS_ENABLE; 308 writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS); 309 310 /* Fixup PCI MSI queue flags */ 311 queue_size = FIELD_GET(PCI_MSI_FLAGS_QMASK, reg); 312 reg |= FIELD_PREP(PCI_MSI_FLAGS_QSIZE, queue_size); 313 writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS); 314 315 /* Fixup MSI addr fields */ 316 writel_relaxed(lower_32_bits(msi->vector_phy), 317 ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_LO); 318 writel_relaxed(upper_32_bits(msi->vector_phy), 319 ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_HI); 320 } 321 322 static inline u32 reg_to_event(u32 reg, struct event_map field) 323 { 324 return (reg & field.reg_mask) ? BIT(field.event_bit) : 0; 325 } 326 327 static u32 pcie_events(struct mc_pcie *port) 328 { 329 u32 reg = readl_relaxed(port->ctrl_base_addr + PCIE_EVENT_INT); 330 u32 val = 0; 331 int i; 332 333 for (i = 0; i < ARRAY_SIZE(pcie_event_to_event); i++) 334 val |= reg_to_event(reg, pcie_event_to_event[i]); 335 336 return val; 337 } 338 339 static u32 sec_errors(struct mc_pcie *port) 340 { 341 u32 reg = readl_relaxed(port->ctrl_base_addr + SEC_ERROR_INT); 342 u32 val = 0; 343 int i; 344 345 for (i = 0; i < ARRAY_SIZE(sec_error_to_event); i++) 346 val |= reg_to_event(reg, sec_error_to_event[i]); 347 348 return val; 349 } 350 351 static u32 ded_errors(struct mc_pcie *port) 352 { 353 u32 reg = readl_relaxed(port->ctrl_base_addr + DED_ERROR_INT); 354 u32 val = 0; 355 int i; 356 357 for (i = 0; i < ARRAY_SIZE(ded_error_to_event); i++) 358 val |= reg_to_event(reg, ded_error_to_event[i]); 359 360 return val; 361 } 362 363 static u32 local_events(struct mc_pcie *port) 364 { 365 u32 reg = readl_relaxed(port->bridge_base_addr + ISTATUS_LOCAL); 366 u32 val = 0; 367 int i; 368 369 for (i = 0; i < ARRAY_SIZE(local_status_to_event); i++) 370 val |= reg_to_event(reg, local_status_to_event[i]); 371 372 return val; 373 } 374 375 static u32 mc_get_events(struct plda_pcie_rp *port) 376 { 377 struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); 378 u32 events = 0; 379 380 events |= pcie_events(mc_port); 381 events |= sec_errors(mc_port); 382 events |= ded_errors(mc_port); 383 events |= local_events(mc_port); 384 385 return events; 386 } 387 388 static irqreturn_t mc_event_handler(int irq, void *dev_id) 389 { 390 struct plda_pcie_rp *port = dev_id; 391 struct device *dev = port->dev; 392 struct irq_data *data; 393 394 data = irq_domain_get_irq_data(port->event_domain, irq); 395 396 if (event_cause[data->hwirq].str) 397 dev_err_ratelimited(dev, "%s\n", event_cause[data->hwirq].str); 398 else 399 dev_err_ratelimited(dev, "bad event IRQ %ld\n", data->hwirq); 400 401 return IRQ_HANDLED; 402 } 403 404 static void mc_ack_event_irq(struct irq_data *data) 405 { 406 struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); 407 struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); 408 u32 event = data->hwirq; 409 void __iomem *addr; 410 u32 mask; 411 412 if (event_descs[event].offset == ISTATUS_LOCAL) 413 addr = mc_port->bridge_base_addr; 414 else 415 addr = mc_port->ctrl_base_addr; 416 417 addr += event_descs[event].offset; 418 mask = event_descs[event].mask; 419 mask |= event_descs[event].enb_mask; 420 421 writel_relaxed(mask, addr); 422 } 423 424 static void mc_mask_event_irq(struct irq_data *data) 425 { 426 struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); 427 struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); 428 u32 event = data->hwirq; 429 void __iomem *addr; 430 u32 mask; 431 u32 val; 432 433 if (event_descs[event].offset == ISTATUS_LOCAL) 434 addr = mc_port->bridge_base_addr; 435 else 436 addr = mc_port->ctrl_base_addr; 437 438 addr += event_descs[event].mask_offset; 439 mask = event_descs[event].mask; 440 if (event_descs[event].enb_mask) { 441 mask <<= PCIE_EVENT_INT_ENB_SHIFT; 442 mask &= PCIE_EVENT_INT_ENB_MASK; 443 } 444 445 if (!event_descs[event].mask_high) 446 mask = ~mask; 447 448 raw_spin_lock(&port->lock); 449 val = readl_relaxed(addr); 450 if (event_descs[event].mask_high) 451 val |= mask; 452 else 453 val &= mask; 454 455 writel_relaxed(val, addr); 456 raw_spin_unlock(&port->lock); 457 } 458 459 static void mc_unmask_event_irq(struct irq_data *data) 460 { 461 struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data); 462 struct mc_pcie *mc_port = container_of(port, struct mc_pcie, plda); 463 u32 event = data->hwirq; 464 void __iomem *addr; 465 u32 mask; 466 u32 val; 467 468 if (event_descs[event].offset == ISTATUS_LOCAL) 469 addr = mc_port->bridge_base_addr; 470 else 471 addr = mc_port->ctrl_base_addr; 472 473 addr += event_descs[event].mask_offset; 474 mask = event_descs[event].mask; 475 476 if (event_descs[event].enb_mask) 477 mask <<= PCIE_EVENT_INT_ENB_SHIFT; 478 479 if (event_descs[event].mask_high) 480 mask = ~mask; 481 482 if (event_descs[event].enb_mask) 483 mask &= PCIE_EVENT_INT_ENB_MASK; 484 485 raw_spin_lock(&port->lock); 486 val = readl_relaxed(addr); 487 if (event_descs[event].mask_high) 488 val &= mask; 489 else 490 val |= mask; 491 writel_relaxed(val, addr); 492 raw_spin_unlock(&port->lock); 493 } 494 495 static struct irq_chip mc_event_irq_chip = { 496 .name = "Microchip PCIe EVENT", 497 .irq_ack = mc_ack_event_irq, 498 .irq_mask = mc_mask_event_irq, 499 .irq_unmask = mc_unmask_event_irq, 500 }; 501 502 static inline void mc_pcie_deinit_clk(void *data) 503 { 504 struct clk *clk = data; 505 506 clk_disable_unprepare(clk); 507 } 508 509 static inline struct clk *mc_pcie_init_clk(struct device *dev, const char *id) 510 { 511 struct clk *clk; 512 int ret; 513 514 clk = devm_clk_get_optional(dev, id); 515 if (IS_ERR(clk)) 516 return clk; 517 if (!clk) 518 return clk; 519 520 ret = clk_prepare_enable(clk); 521 if (ret) 522 return ERR_PTR(ret); 523 524 devm_add_action_or_reset(dev, mc_pcie_deinit_clk, clk); 525 526 return clk; 527 } 528 529 static int mc_pcie_init_clks(struct device *dev) 530 { 531 int i; 532 struct clk *fic; 533 534 /* 535 * PCIe may be clocked via Fabric Interface using between 1 and 4 536 * clocks. Scan DT for clocks and enable them if present 537 */ 538 for (i = 0; i < ARRAY_SIZE(poss_clks); i++) { 539 fic = mc_pcie_init_clk(dev, poss_clks[i]); 540 if (IS_ERR(fic)) 541 return PTR_ERR(fic); 542 } 543 544 return 0; 545 } 546 547 static int mc_request_event_irq(struct plda_pcie_rp *plda, int event_irq, 548 int event) 549 { 550 return devm_request_irq(plda->dev, event_irq, mc_event_handler, 551 0, event_cause[event].sym, plda); 552 } 553 554 static const struct plda_event_ops mc_event_ops = { 555 .get_events = mc_get_events, 556 }; 557 558 static const struct plda_event mc_event = { 559 .request_event_irq = mc_request_event_irq, 560 .intx_event = EVENT_LOCAL_PM_MSI_INT_INTX, 561 .msi_event = EVENT_LOCAL_PM_MSI_INT_MSI, 562 }; 563 564 static inline void mc_clear_secs(struct mc_pcie *port) 565 { 566 writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, 567 port->ctrl_base_addr + SEC_ERROR_INT); 568 writel_relaxed(0, port->ctrl_base_addr + SEC_ERROR_EVENT_CNT); 569 } 570 571 static inline void mc_clear_deds(struct mc_pcie *port) 572 { 573 writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, 574 port->ctrl_base_addr + DED_ERROR_INT); 575 writel_relaxed(0, port->ctrl_base_addr + DED_ERROR_EVENT_CNT); 576 } 577 578 static void mc_disable_interrupts(struct mc_pcie *port) 579 { 580 u32 val; 581 582 /* Ensure ECC bypass is enabled */ 583 val = ECC_CONTROL_TX_RAM_ECC_BYPASS | 584 ECC_CONTROL_RX_RAM_ECC_BYPASS | 585 ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS | 586 ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS; 587 writel_relaxed(val, port->ctrl_base_addr + ECC_CONTROL); 588 589 /* Disable SEC errors and clear any outstanding */ 590 writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, 591 port->ctrl_base_addr + SEC_ERROR_INT_MASK); 592 mc_clear_secs(port); 593 594 /* Disable DED errors and clear any outstanding */ 595 writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, 596 port->ctrl_base_addr + DED_ERROR_INT_MASK); 597 mc_clear_deds(port); 598 599 /* Disable local interrupts and clear any outstanding */ 600 writel_relaxed(0, port->bridge_base_addr + IMASK_LOCAL); 601 writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_LOCAL); 602 writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_MSI); 603 604 /* Disable PCIe events and clear any outstanding */ 605 val = PCIE_EVENT_INT_L2_EXIT_INT | 606 PCIE_EVENT_INT_HOTRST_EXIT_INT | 607 PCIE_EVENT_INT_DLUP_EXIT_INT | 608 PCIE_EVENT_INT_L2_EXIT_INT_MASK | 609 PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK | 610 PCIE_EVENT_INT_DLUP_EXIT_INT_MASK; 611 writel_relaxed(val, port->ctrl_base_addr + PCIE_EVENT_INT); 612 613 /* Disable host interrupts and clear any outstanding */ 614 writel_relaxed(0, port->bridge_base_addr + IMASK_HOST); 615 writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_HOST); 616 } 617 618 static void mc_pcie_setup_inbound_atr(struct mc_pcie *port, int window_index, 619 u64 axi_addr, u64 pcie_addr, u64 size) 620 { 621 u32 table_offset = window_index * ATR_ENTRY_SIZE; 622 void __iomem *table_addr = port->bridge_base_addr + table_offset; 623 u32 atr_sz; 624 u32 val; 625 626 atr_sz = ilog2(size) - 1; 627 628 val = ALIGN_DOWN(lower_32_bits(pcie_addr), SZ_4K); 629 val |= FIELD_PREP(ATR_SIZE_MASK, atr_sz); 630 val |= ATR_IMPL_ENABLE; 631 632 writel(val, table_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); 633 634 writel(upper_32_bits(pcie_addr), table_addr + ATR0_PCIE_WIN0_SRC_ADDR); 635 636 writel(lower_32_bits(axi_addr), table_addr + ATR0_PCIE_WIN0_TRSL_ADDR_LSB); 637 writel(upper_32_bits(axi_addr), table_addr + ATR0_PCIE_WIN0_TRSL_ADDR_UDW); 638 639 writel(TRSL_ID_AXI4_MASTER_0, table_addr + ATR0_PCIE_WIN0_TRSL_PARAM); 640 } 641 642 static int mc_pcie_setup_inbound_ranges(struct platform_device *pdev, 643 struct mc_pcie *port) 644 { 645 struct device *dev = &pdev->dev; 646 struct device_node *dn = dev->of_node; 647 struct of_range_parser parser; 648 struct of_range range; 649 int atr_index = 0; 650 651 /* 652 * MPFS PCIe Root Port is 32-bit only, behind a Fabric Interface 653 * Controller FPGA logic block which contains the AXI-S interface. 654 * 655 * From the point of view of the PCIe Root Port, there are only two 656 * supported Root Port configurations: 657 * 658 * Configuration 1: for use with fully coherent designs; supports a 659 * window from 0x0 (CPU space) to specified PCIe space. 660 * 661 * Configuration 2: for use with non-coherent designs; supports two 662 * 1 GB windows to CPU space; one mapping CPU space 0 to PCIe space 663 * 0x80000000 and a second mapping CPU space 0x40000000 to PCIe 664 * space 0xc0000000. This cfg needs two windows because of how the 665 * MSI space is allocated in the AXI-S range on MPFS. 666 * 667 * The FIC interface outside the PCIe block *must* complete the 668 * inbound address translation as per MCHP MPFS FPGA design 669 * guidelines. 670 */ 671 if (device_property_read_bool(dev, "dma-noncoherent")) { 672 /* 673 * Always need same two tables in this case. Need two tables 674 * due to hardware interactions between address and size. 675 */ 676 mc_pcie_setup_inbound_atr(port, 0, 0, 677 MPFS_NC_BOUNCE_ADDR, SZ_1G); 678 mc_pcie_setup_inbound_atr(port, 1, SZ_1G, 679 MPFS_NC_BOUNCE_ADDR + SZ_1G, SZ_1G); 680 } else { 681 /* Find any DMA ranges */ 682 if (of_pci_dma_range_parser_init(&parser, dn)) { 683 /* No DMA range property - setup default */ 684 mc_pcie_setup_inbound_atr(port, 0, 0, 0, SZ_4G); 685 return 0; 686 } 687 688 for_each_of_range(&parser, &range) { 689 if (atr_index >= MC_MAX_NUM_INBOUND_WINDOWS) { 690 dev_err(dev, "too many inbound ranges; %d available tables\n", 691 MC_MAX_NUM_INBOUND_WINDOWS); 692 return -EINVAL; 693 } 694 mc_pcie_setup_inbound_atr(port, atr_index, 0, 695 range.pci_addr, range.size); 696 atr_index++; 697 } 698 } 699 700 return 0; 701 } 702 703 static int mc_platform_init(struct pci_config_window *cfg) 704 { 705 struct device *dev = cfg->parent; 706 struct platform_device *pdev = to_platform_device(dev); 707 struct pci_host_bridge *bridge = platform_get_drvdata(pdev); 708 int ret; 709 710 /* Configure address translation table 0 for PCIe config space */ 711 plda_pcie_setup_window(port->bridge_base_addr, 0, cfg->res.start, 712 cfg->res.start, 713 resource_size(&cfg->res)); 714 715 /* Need some fixups in config space */ 716 mc_pcie_enable_msi(port, cfg->win); 717 718 /* Configure non-config space outbound ranges */ 719 ret = plda_pcie_setup_iomems(bridge, &port->plda); 720 if (ret) 721 return ret; 722 723 ret = mc_pcie_setup_inbound_ranges(pdev, port); 724 if (ret) 725 return ret; 726 727 port->plda.event_ops = &mc_event_ops; 728 port->plda.event_irq_chip = &mc_event_irq_chip; 729 port->plda.events_bitmap = GENMASK(NUM_EVENTS - 1, 0); 730 731 /* Address translation is up; safe to enable interrupts */ 732 ret = plda_init_interrupts(pdev, &port->plda, &mc_event); 733 if (ret) 734 return ret; 735 736 return 0; 737 } 738 739 static int mc_host_probe(struct platform_device *pdev) 740 { 741 struct device *dev = &pdev->dev; 742 void __iomem *apb_base_addr; 743 struct plda_pcie_rp *plda; 744 int ret; 745 u32 val; 746 747 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 748 if (!port) 749 return -ENOMEM; 750 751 plda = &port->plda; 752 plda->dev = dev; 753 754 port->bridge_base_addr = devm_platform_ioremap_resource_byname(pdev, 755 "bridge"); 756 port->ctrl_base_addr = devm_platform_ioremap_resource_byname(pdev, 757 "ctrl"); 758 if (!IS_ERR(port->bridge_base_addr) && !IS_ERR(port->ctrl_base_addr)) 759 goto addrs_set; 760 761 /* 762 * The original, incorrect, binding that lumped the control and 763 * bridge addresses together still needs to be handled by the driver. 764 */ 765 apb_base_addr = devm_platform_ioremap_resource_byname(pdev, "apb"); 766 if (IS_ERR(apb_base_addr)) 767 return dev_err_probe(dev, PTR_ERR(apb_base_addr), 768 "both legacy apb register and ctrl/bridge regions missing"); 769 770 port->bridge_base_addr = apb_base_addr + MC_PCIE1_BRIDGE_ADDR; 771 port->ctrl_base_addr = apb_base_addr + MC_PCIE1_CTRL_ADDR; 772 773 addrs_set: 774 mc_disable_interrupts(port); 775 776 plda->bridge_addr = port->bridge_base_addr; 777 plda->num_events = NUM_EVENTS; 778 779 /* Allow enabling MSI by disabling MSI-X */ 780 val = readl(port->bridge_base_addr + PCIE_PCI_IRQ_DW0); 781 val &= ~MSIX_CAP_MASK; 782 writel(val, port->bridge_base_addr + PCIE_PCI_IRQ_DW0); 783 784 /* Pick num vectors from bitfile programmed onto FPGA fabric */ 785 val = readl(port->bridge_base_addr + PCIE_PCI_IRQ_DW0); 786 val &= NUM_MSI_MSGS_MASK; 787 val >>= NUM_MSI_MSGS_SHIFT; 788 789 plda->msi.num_vectors = 1 << val; 790 791 /* Pick vector address from design */ 792 plda->msi.vector_phy = readl_relaxed(port->bridge_base_addr + IMSI_ADDR); 793 794 ret = mc_pcie_init_clks(dev); 795 if (ret) { 796 dev_err(dev, "failed to get clock resources, error %d\n", ret); 797 return -ENODEV; 798 } 799 800 return pci_host_common_probe(pdev); 801 } 802 803 static const struct pci_ecam_ops mc_ecam_ops = { 804 .init = mc_platform_init, 805 .pci_ops = { 806 .map_bus = pci_ecam_map_bus, 807 .read = pci_generic_config_read, 808 .write = pci_generic_config_write, 809 } 810 }; 811 812 static const struct of_device_id mc_pcie_of_match[] = { 813 { 814 .compatible = "microchip,pcie-host-1.0", 815 .data = &mc_ecam_ops, 816 }, 817 {}, 818 }; 819 820 MODULE_DEVICE_TABLE(of, mc_pcie_of_match); 821 822 static struct platform_driver mc_pcie_driver = { 823 .probe = mc_host_probe, 824 .driver = { 825 .name = "microchip-pcie", 826 .of_match_table = mc_pcie_of_match, 827 .suppress_bind_attrs = true, 828 }, 829 }; 830 831 builtin_platform_driver(mc_pcie_driver); 832 MODULE_LICENSE("GPL"); 833 MODULE_DESCRIPTION("Microchip PCIe host controller driver"); 834 MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>"); 835