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/qemu/hw/display/
H A Ddm163.c2 * QEMU DM163 8x3-channel constant current led driver
6 * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
7 * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
9 * SPDX-License-Identifier: GPL-2.0-or-later
14 * http://www.siti.com.tw/product/spec/LED/DM163.pdf
21 #include "hw/qdev-properties.h"
28 #define ROW_PERSISTENCE 3
29 #define TURNED_OFF_ROW (COLOR_BUFFER_SIZE - 1)
36 VMSTATE_UINT64_ARRAY(bank0_shift_register, DM163State, 3),
37 VMSTATE_UINT64_ARRAY(bank1_shift_register, DM163State, 3),
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H A Djazz_led.c2 * QEMU JAZZ LED emulator.
4 * Copyright (c) 2007-2012 Herve Poussineau
38 #define TYPE_JAZZ_LED "jazz-led"
56 val = s->segments; in jazz_led_read()
70 s->segments = new_val; in jazz_led_write()
71 s->state |= REDRAW_SEGMENTS; in jazz_led_write()
92 bpp = (surface_bits_per_pixel(ds) + 7) >> 3; in draw_horizontal_line()
123 bpp = (surface_bits_per_pixel(ds) + 7) >> 3; in draw_vertical_line()
150 DisplaySurface *surface = qemu_console_surface(s->con); in jazz_led_update_display()
155 if (s->state & REDRAW_BACKGROUND) { in jazz_led_update_display()
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H A Dtrace-events27 vmware_update_rect_delayed_flush(void) "display update FIFO full - forcing flush"
29 # virtio-gpu-base.c
32 # virtio-gpu-3d.c
33 # virtio-gpu.c
56 virtio_gpu_inc_inflight_fences(uint32_t inflight) "in-flight+ %u"
57 virtio_gpu_dec_inflight_fences(uint32_t inflight) "in-flight- %u"
81 …_t slot_id, uint64_t guest_start, uint64_t guest_end) "%d %u: guest phys 0x%"PRIx64 " - 0x%" PRIx64
121 # qxl-render.c
145 ati_mm_read(unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"PRIx64 " %s -…
146 …unsigned int size, uint64_t addr, const char *name, uint64_t val) "%u 0x%"PRIx64 " %s <- 0x%"PRIx64
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/qemu/docs/interop/
H A Dvnc-ledstate-pseudo-encoding.rst1 VNC LED state Pseudo-encoding
5 ------------
7 This document describes the Pseudo-encoding of LED state for RFB which
10 http://tigervnc.svn.sourceforge.net/viewvc/tigervnc/rfbproto/rfbproto.rst?content-type=text/plain
13 between the lock keys notification LED on the computer running the VNC
17 To solve this problem it attempts to add LED state Pseudo-encoding
18 extension to VNC protocol to deal with setting LED state.
20 Pseudo-encoding
21 ---------------
23 This Pseudo-encoding requested by client declares to server that it supports
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/qemu/hw/gpio/
H A Dpca9552.c2 * PCA9552 I2C LED blinker
4 * https://www.nxp.com/docs/en/application-note/AN264.pdf
6 * Copyright (c) 2017-2018, IBM Corporation.
7 * Copyright (c) 2020 Philippe Mathieu-Daudé
10 * later. See the COPYING file in the top-level directory.
17 #include "hw/qdev-properties.h"
57 return extract32(s->regs[reg], shift, 2); in pca955x_pin_get_config()
63 return (s->regs[PCA9552_INPUT1] << 8) | s->regs[PCA9552_INPUT0]; in pca955x_pins_get_status()
81 for (i = 0; i < k->pin_count; i++) { in pca955x_display_pins_status()
89 trace_pca955x_gpio_status(s->description, buf); in pca955x_display_pins_status()
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/qemu/hw/misc/
H A Dmps2-scc.c29 #include "hw/misc/mps2-scc.h"
30 #include "hw/misc/led.h"
31 #include "hw/qdev-properties.h"
60 return extract32(s->id, 4, 8); in scc_partno()
116 if (function != 1 || device >= s->num_oscclk) { in scc_cfg_write()
123 s->oscclk[device] = value; in scc_cfg_write()
134 if (function != 1 || device >= s->num_oscclk) { in scc_cfg_read()
141 *value = s->oscclk[device]; in scc_cfg_read()
154 r = s->cfg0; in mps2_scc_read()
157 r = s->cfg1; in mps2_scc_read()
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H A Dmps2-fpgaio.c26 #include "hw/misc/mps2-fpgaio.h"
27 #include "hw/misc/led.h"
28 #include "hw/qdev-properties.h"
44 return muldiv64(now - tick_offset, frq, NANOSECONDS_PER_SECOND); in counter_from_tickoff()
49 return now - muldiv64(count, NANOSECONDS_PER_SECOND, frq); in tickoff_from_counter()
55 * Update s->counter and s->pscntr to their true current values in resync_counter()
60 int64_t elapsed = now - s->pscntr_sync_ticks; in resync_counter()
66 uint64_t ticks = muldiv64(elapsed, s->prescale_clk, NANOSECONDS_PER_SECOND); in resync_counter()
70 * PSCNTR reloads from PRESCALE one tick-period after it hits zero, in resync_counter()
76 } else if (ticks < s->pscntr) { in resync_counter()
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H A Darm_integrator_debug.c2 * LED, Switch and Debug control registers for ARM Integrator Boards
9 …//developer.arm.com/documentation/dui0159/b/peripherals-and-interfaces/debug-leds-and-dip-switch-i…
14 * See the COPYING file in the top-level directory.
57 case 3: /* SWITCHES */ in intdbg_control_write()
83 memory_region_init_io(&s->iomem, obj, &intdbg_control_ops, in intdbg_control_init()
84 NULL, "dbg-leds", 0x1000000); in intdbg_control_init()
85 sysbus_init_mmio(sd, &s->iomem); in intdbg_control_init()
H A Darm_sysctl.c4 * Copyright (c) 2006-2007 CodeSourcery.
12 #include "hw/qdev-properties.h"
72 VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
93 return (s->sys_id >> 16) & 0xfff; in board_id()
101 s->leds = 0; in arm_sysctl_reset()
102 s->lockval = 0; in arm_sysctl_reset()
103 s->cfgdata1 = 0; in arm_sysctl_reset()
104 s->cfgdata2 = 0; in arm_sysctl_reset()
105 s->flags = 0; in arm_sysctl_reset()
106 s->resetlevel = 0; in arm_sysctl_reset()
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/qemu/hw/net/
H A De1000_regs.h4 Copyright(c) 1999 - 2006 Intel Corporation.
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
37 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
38 #define E1000_EIAC 0x000DC /* Ext. Interrupt Auto Clear - RW */
39 #define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
40 #define E1000_EITR 0x000E8 /* Extended Interrupt Throttling Rate - RW */
41 #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
42 #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
43 #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
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H A De1000x_regs.h4 Copyright(c) 1999 - 2006 Intel Corporation.
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
115 * RW - register is both readable and writable
116 * RO - register is read only
117 * WO - register is write only
118 * R/clr - register is read only and is cleared when read
119 * A - register array
121 #define E1000_CTRL 0x00000 /* Device Control - RW */
122 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
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/qemu/include/hw/gpio/
H A Dpca9552_regs.h2 * PCA9552 I2C LED blinker registers
4 * Copyright (c) 2017-2018, IBM Corporation.
7 * later. See the COPYING file in the top-level directory.
13 * Bits [0:3] are used to address a specific register.
18 #define PCA9552_PWM0 3 /* read/write PWM register 0 */
27 * Bit [4] is used to activate the Auto-Increment option of the
/qemu/include/hw/display/
H A Ddm163.h2 * QEMU DM163 8x3-channel constant current led driver
6 * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
7 * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
9 * SPDX-License-Identifier: GPL-2.0-or-later
16 #include "hw/qdev-core.h"
23 #define DM163_NUM_LEDS (RGB_MATRIX_NUM_COLS * 3)
31 uint64_t bank0_shift_register[3];
32 uint64_t bank1_shift_register[3];
/qemu/hw/m68k/
H A Dnext-cube.c5 * Copyright (c) 2024 Mark Cave-Ayland
15 #include "exec/cpu-interrupt.h"
19 #include "hw/m68k/next-cube.h"
28 #include "hw/qdev-properties.h"
30 #include "qemu/error-report.h"
48 #define TYPE_NEXT_RTC "next-rtc"
66 #define TYPE_NEXT_SCSI "next-scsi"
82 #define TYPE_NEXT_PC "next-pc"
102 uint32_t led; member
133 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube")
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/qemu/hw/input/
H A Dadb-kbd.c30 #include "hw/input/adb-keys.h"
31 #include "adb-internal.h"
182 if (s->count < sizeof(s->data)) { in adb_kbd_put_keycode()
183 s->data[s->wptr] = keycode; in adb_kbd_put_keycode()
184 if (++s->wptr == sizeof(s->data)) { in adb_kbd_put_keycode()
185 s->wptr = 0; in adb_kbd_put_keycode()
187 s->count++; in adb_kbd_put_keycode()
196 if (s->count == 0) { in adb_kbd_poll()
199 keycode = s->data[s->rptr]; in adb_kbd_poll()
200 s->rptr++; in adb_kbd_poll()
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H A Dhid.c77 return hs->n > 0 || hs->idle_pending; in hid_has_events()
84 hs->idle_pending = true; in hid_idle_timer()
85 hs->event(hs); in hid_idle_timer()
90 if (hs->idle_timer) { in hid_del_idle_timer()
91 timer_free(hs->idle_timer); in hid_del_idle_timer()
92 hs->idle_timer = NULL; in hid_del_idle_timer()
98 if (hs->idle) { in hid_set_next_idle()
100 NANOSECONDS_PER_SECOND * hs->idle * 4 / 1000; in hid_set_next_idle()
101 if (!hs->idle_timer) { in hid_set_next_idle()
102 hs->idle_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hid_idle_timer, hs); in hid_set_next_idle()
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/qemu/include/hw/ppc/
H A Dspapr_drc.h10 * See the COPYING file in the top-level directory.
19 #include "hw/qdev-core.h"
22 #define TYPE_SPAPR_DR_CONNECTOR "spapr-dr-connector"
31 #define TYPE_SPAPR_DRC_PHYSICAL "spapr-drc-physical"
35 #define TYPE_SPAPR_DRC_LOGICAL "spapr-drc-logical"
37 #define TYPE_SPAPR_DRC_CPU "spapr-drc-cpu"
39 #define TYPE_SPAPR_DRC_PCI "spapr-drc-pci"
41 #define TYPE_SPAPR_DRC_LMB "spapr-drc-lmb"
43 #define TYPE_SPAPR_DRC_PHB "spapr-drc-phb"
45 #define TYPE_SPAPR_DRC_PMEM "spapr-drc-pmem"
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/qemu/tests/qtest/fuzz/
H A Dvirtio_net_fuzz.c2 * virtio-net Fuzzing Target
10 * See the COPYING file in the top-level directory.
15 #include "standard-headers/linux/virtio_config.h"
17 #include "tests/qtest/libqos/virtio-net.h"
46 QVirtioDevice *dev = net_if->vdev; in virtio_net_fuzz_multi()
52 Size -= sizeof(vqa); in virtio_net_fuzz_multi()
54 q = net_if->queues[vqa.queue % 3]; in virtio_net_fuzz_multi()
70 * trivial asserion failure on zero-zied buffer in virtio_net_fuzz_multi()
90 * must manually run the main-loop for all the bhs to run, we use in virtio_net_fuzz_multi()
93 while (!vqa.rx && q != net_if->queues[QVIRTIO_RX_VQ]) { in virtio_net_fuzz_multi()
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/qemu/hw/mips/
H A Djazz.c4 * Copyright (c) 2007-2008 Hervé Poussineau
31 #include "hw/char/serial-mm.h"
43 #include "hw/display/bochs-vbe.h"
50 #include "qemu/error-report.h"
53 #include "accel/tcg/cpu-ops.h"
145 prom[i] = nd->macaddr.a[i]; in mips_jazz_init_net()
151 prom[7] = 0xff - checksum; in mips_jazz_init_net()
201 if (machine->ram_size > 256 * MiB) { in mips_jazz_init()
206 cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); in mips_jazz_init()
211 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, in mips_jazz_init()
[all …]
/qemu/hw/arm/
H A Dintegratorcp.c4 * Copyright (c) 2005-2007 CodeSourcery.
19 #include "system/address-spaces.h"
23 #include "qemu/error-report.h"
30 #include "target/arm/cpu-qom.h"
98 return s->cm_osc; in integratorcm_read()
99 case 3: /* CM_CTRL */ in integratorcm_read()
100 return s->cm_ctrl; in integratorcm_read()
104 if (s->cm_lock == 0xa05f) { in integratorcm_read()
107 return s->cm_lock; in integratorcm_read()
113 return s->cm_auxosc; in integratorcm_read()
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H A Daspeed.c9 * the COPYING file in the top-level directory.
24 #include "hw/misc/led.h"
25 #include "hw/qdev-properties.h"
26 #include "system/block-backend.h"
29 #include "qemu/error-report.h"
32 #include "hw/qdev-clock.h"
36 .board_id = -1, /* device-tree-only board */
53 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
166 /* Quanta-Q71l hardware value */
204 /* Qualcomm DC-SCM hardware value */
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H A Domap1.c4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
9 * (at your option) version 3 of the License.
22 #include "qemu/error-report.h"
23 #include "qemu/main-loop.h"
26 #include "system/address-spaces.h"
29 #include "hw/qdev-properties.h"
44 #include "target/arm/cpu-qom.h"
49 qemu_log_mask(LOG_GUEST_ERROR, "%s: %d-bit register %#08" HWADDR_PRIx "\n", in omap_log_badwidth()
127 uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time; in omap_timer_read()
129 if (timer->st && timer->enable && timer->rate) in omap_timer_read()
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/qemu/include/hw/arm/
H A Domap.h4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
9 * (at your option) version 3 of the License.
24 #include "target/arm/cpu-qom.h"
62 #define TYPE_OMAP_INTC "omap-intc"
94 #define TYPE_OMAP1_GPIO "omap-gpio"
104 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
107 #define OMAP_INT_FIQ 3
130 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
137 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
145 * OMAP-310 specific IRQ numbers for level 1 interrupt handler
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/qemu/linux-user/
H A Dsyscall_defs.h16 #define TARGET_SYS_CONNECT 3 /* connect() */
38 #define IPCOP_semctl 3
91 #define TARGET_IOC_DIRBITS 3
118 #define TARGET_IOC_NRMASK ((1 << TARGET_IOC_NRBITS)-1)
119 #define TARGET_IOC_TYPEMASK ((1 << TARGET_IOC_TYPEBITS)-1)
120 #define TARGET_IOC_SIZEMASK ((1 << TARGET_IOC_SIZEBITS)-1)
121 #define TARGET_IOC_DIRMASK ((1 << TARGET_IOC_DIRBITS)-1)
180 uint8_t __pad[sizeof(struct target_sockaddr) -
181 sizeof(abi_ushort) - sizeof(abi_short) -
283 abi_long constant; /* PLL (phase-locked loop) time constant */
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/qemu/include/hw/misc/macio/
H A Dpmu.h25 #define PMU_ADB_POLL_OFF 0x21 /* disable ADB auto-poll */
26 #define PMU_WRITE_NVRAM 0x33 /* write non-volatile RAM */
27 #define PMU_READ_NVRAM 0x3b /* read non-volatile RAM */
28 #define PMU_SET_RTC 0x30 /* set real-time clock */
29 #define PMU_READ_RTC 0x38 /* read real-time clock */
33 #define PMU_PCEJECT 0x4c /* eject PC-card from slot */
41 #define PMU_POWER_EVENTS 0x8f /* Send power-event commands to PMU */
62 #define PMU_POW_IRLED 0x04 /* IR led power (on wallstreet) */
67 #define PMU_INT_PCEJECT 0x04 /* PC-card eject buttons */
72 #define PMU_INT_TICK 0x80 /* 1-second tick interrupt */
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