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/qemu/util/
H A Dint128.c42 uint64_t hi, lo, tmp; in divrem128() local
43 int s = clz64(v.hi); in divrem128()
47 hi = u.hi; in divrem128()
49 tmp = divu128(&lo, &hi, v.lo); in divrem128()
50 *q = int128_make128(lo, hi); in divrem128()
53 hi = int128_gethi(int128_lshift(v, s)); in divrem128()
55 if (hi > u.hi) { in divrem128()
57 tmp = u.hi; in divrem128()
58 divu128(&lo, &tmp, hi); in divrem128()
62 tmp = u.hi - hi; in divrem128()
[all …]
/qemu/include/qemu/
H A Dint128.h25 static inline Int128 int128_make128(uint64_t lo, uint64_t hi) in int128_make128() argument
27 return (__uint128_t)hi << 64 | lo; in int128_make128()
240 int64_t hi; member
244 int64_t hi;
250 return (Int128) { .lo = a, .hi = 0 }; in int128_make64()
255 return (Int128) { .lo = a, .hi = a >> 63 }; in int128_makes64()
258 static inline Int128 int128_make128(uint64_t lo, uint64_t hi) in int128_make128() argument
260 return (Int128) { .lo = lo, .hi = hi }; in int128_make128()
265 assert(!a.hi); in int128_get64()
276 return a.hi; in int128_gethi()
[all …]
/qemu/tests/tcg/mips/user/isa/r5900/
H A Dtest_r5900_maddu.c12 uint32_t hi = a >> 32; in maddu() local
22 : "=r" (rd), "=r" (lo), "=r" (hi) in maddu()
23 : "r" (rs), "r" (rt), "r" (lo), "r" (hi)); in maddu()
24 r = ((uint64_t)hi << 32) | (uint32_t)lo; in maddu()
35 uint32_t hi = a >> 32; in maddu1() local
45 : "=r" (rd), "=r" (lo), "=r" (hi) in maddu1()
46 : "r" (rs), "r" (rt), "r" (lo), "r" (hi)); in maddu1()
47 r = ((uint64_t)hi << 32) | (uint32_t)lo; in maddu1()
H A Dtest_r5900_madd.c12 int32_t hi = a >> 32; in madd() local
22 : "=r" (rd), "=r" (lo), "=r" (hi) in madd()
23 : "r" (rs), "r" (rt), "r" (lo), "r" (hi)); in madd()
24 r = ((int64_t)hi << 32) | (uint32_t)lo; in madd()
35 int32_t hi = a >> 32; in madd1() local
45 : "=r" (rd), "=r" (lo), "=r" (hi) in madd1()
46 : "r" (rs), "r" (rt), "r" (lo), "r" (hi)); in madd1()
47 r = ((int64_t)hi << 32) | (uint32_t)lo; in madd1()
H A Dtest_r5900_multu.c11 uint32_t rd, lo, hi; in multu() local
18 : "=r" (rd), "=r" (lo), "=r" (hi) in multu()
20 r = ((uint64_t)hi << 32) | (uint32_t)lo; in multu()
30 uint32_t rd, lo, hi; in multu1() local
37 : "=r" (rd), "=r" (lo), "=r" (hi) in multu1()
39 r = ((uint64_t)hi << 32) | (uint32_t)lo; in multu1()
H A Dtest_r5900_mult.c11 int32_t rd, lo, hi; in mult() local
18 : "=r" (rd), "=r" (lo), "=r" (hi) in mult()
20 r = ((int64_t)hi << 32) | (uint32_t)lo; in mult()
30 int32_t rd, lo, hi; in mult1() local
37 : "=r" (rd), "=r" (lo), "=r" (hi) in mult1()
39 r = ((int64_t)hi << 32) | (uint32_t)lo; in mult1()
H A Dtest_r5900_mflohi1.c13 int64_t lo, hi, lo1, hi1; in main() local
16 /* Test both LO/HI and LO1/HI1 to verify separation. */ in main()
24 : "=r" (lo), "=r" (hi), in main()
28 r = ((int64_t)hi << 32) | (uint32_t)lo; in main()
H A Dtest_r5900_divu1.c13 uint32_t lo, hi; in divu1() local
19 : "=r" (lo), "=r" (hi) in divu1()
23 assert(rs % rt == hi); in divu1()
25 return (struct quotient_remainder) { .quotient = lo, .remainder = hi }; in divu1()
H A Dtest_r5900_div1.c13 int32_t lo, hi; in div1() local
19 : "=r" (lo), "=r" (hi) in div1()
23 assert(rs % rt == hi); in div1()
25 return (struct quotient_remainder) { .quotient = lo, .remainder = hi }; in div1()
/qemu/target/mips/tcg/
H A Dvr54xx_translate.c22 * MACCHI Multiply, accumulate, and move HI
23 * MACCHIU Unsigned multiply, accumulate, and move HI
26 * MSACHI Multiply, negate, accumulate, and move HI
27 * MSACHIU Unsigned multiply, negate, accumulate, and move HI
29 * MULHI Multiply and move HI
30 * MULHIU Unsigned multiply and move HI
32 * MULSHI Multiply, negate, and move HI
33 * MULSHIU Unsigned multiply, negate, and move HI
H A Ddsp_helper.c256 temp = ((uint64_t)env->active_tc.HI[acc] << 32) | in mipsdsp_sat32_acc_q31()
281 /* a[0] is LO, a[1] is HI. */
290 ret[1] = env->active_tc.HI[ac] + a[1]; in mipsdsp_sat64_acc_add_q63()
317 ret[1] = env->active_tc.HI[ac] - a[1]; in mipsdsp_sat64_acc_sub_q63()
502 /* 128 bits long. p[0] is LO, p[1] is HI. */
510 acc = ((int64_t)env->active_tc.HI[ac] << 32) | in mipsdsp_rndrashift_short_acc()
517 /* 128 bits long. p[0] is LO, p[1] is HI */
525 tempB = env->active_tc.HI[ac]; in mipsdsp_rashift_acc()
538 /* 128 bits long. p[0] is LO, p[1] is HI , p[2] is sign of HI.*/
546 tempB = env->active_tc.HI[ac]; in mipsdsp_rndrashift_acc()
[all …]
H A Dvr54xx_helper.c29 return ((uint64_t)(env->active_tc.HI[0]) << 32) | in get_HILO()
36 return env->active_tc.HI[0] = (int32_t)(HILO >> 32); in set_HIT0_LO()
42 env->active_tc.HI[0] = (int32_t)(HILO >> 32); in set_HI_LOT0()
/qemu/tests/tcg/tricore/c/
H A Dcrt0-tc2x.S57 movh.a %sp,hi:__USTACK # load %sp
59 movh %d0,hi:__ISTACK # load $isp
66 movh %d0,hi:first_trap_table #; load $btv
96 movh.a %a0,hi:_SMALL_DATA_ # %a0 addresses .sdata/.sbss
98 movh.a %a1,hi:_SMALL_DATA2_ # %a1 addresses .sdata2/.sbss2
100 movh.a %a8,hi:_SMALL_DATA3_ # %a8 addresses .sdata3/.sbss3
102 movh.a %a9,hi:_SMALL_DATA4_ # %a9 addresses .sdata4/.sbss4
163 movh %d0,hi:__CSA_BEGIN #; %d0 = begin of CSA
167 movh %d2,hi:__CSA_END #; %d2 = end of CSA
213 movh.a %a13,hi:__clear_table # %a13 = &first table entry
[all …]
/qemu/hw/i386/
H A Dtrace-events7 vtd_inv_desc(const char *type, uint64_t hi, uint64_t lo) "invalidate desc type %s high 0x%"PRIx64" …
19 vtd_inv_desc_wait_write_fail(uint64_t hi, uint64_t lo) "write fail for wait desc hi 0x%"PRIx64" lo …
35 …nt16_t domain, uint64_t hi, uint64_t lo) "%s: replay valid context device %02"PRIx8":%02"PRIx8".%0…
60 vtd_ir_irte_get(int index, uint64_t lo, uint64_t hi) "index %d low 0x%"PRIx64" high 0x%"PRIx64
67 vtd_frr_new(int index, uint64_t hi, uint64_t lo) "index %d high 0x%"PRIx64" low 0x%"PRIx64
112 amdvi_ir_irte_ga_val(uint64_t hi, uint64_t lo) "hi 0x%"PRIx64" lo 0x%"PRIx64
H A Dintel_iommu.c540 uint64_t hi, uint64_t lo) in vtd_record_frcd() argument
547 vtd_set_quad_raw(s, frcd_reg_addr + 8, hi); in vtd_record_frcd()
549 trace_vtd_frr_new(index, hi, lo); in vtd_record_frcd()
572 uint64_t hi, uint64_t lo) in vtd_report_frcd_fault() argument
595 vtd_record_frcd(s, s->next_frcd_reg, hi, lo); in vtd_report_frcd_fault()
626 uint64_t hi, lo; in vtd_report_dmar_fault() local
633 hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault) | in vtd_report_dmar_fault()
636 hi |= VTD_FRCD_T; in vtd_report_dmar_fault()
639 vtd_report_frcd_fault(s, source_id, hi, lo); in vtd_report_dmar_fault()
646 uint64_t hi, lo; in vtd_report_ir_fault() local
[all …]
/qemu/hw/core/
H A Dmachine-hmp-cmds.c260 HvBalloonDeviceInfo *hi; in hmp_info_memory_devices() local
319 hi = value->u.hv_balloon.data; in hmp_info_memory_devices()
322 hi->id ? hi->id : ""); in hmp_info_memory_devices()
323 if (hi->has_memaddr) { in hmp_info_memory_devices()
325 hi->memaddr); in hmp_info_memory_devices()
327 monitor_printf(mon, " max-size: %" PRIu64 "\n", hi->max_size); in hmp_info_memory_devices()
328 if (hi->memdev) { in hmp_info_memory_devices()
329 monitor_printf(mon, " memdev: %s\n", hi->memdev); in hmp_info_memory_devices()
/qemu/target/ppc/translate/
H A Dvmx-impl.c.inc882 TCGv_i64 hi, lo, t0, t1, n, zero = tcg_constant_i64(0);
887 hi = tcg_temp_new_i64();
892 get_avr64(hi, a->vra, true);
898 tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, hi, lo);
905 tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, t1, hi);
907 tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, lo, hi);
914 tcg_gen_sar_i64(t0, hi, n);
916 tcg_gen_shr_i64(t0, hi, n);
926 tcg_gen_shl_i64(hi, hi, n);
930 tcg_gen_shl_i64(hi, hi, n);
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H A Dfixedpoint-impl.c.inc74 TCGv_i64 lo, hi;
99 hi = cpu_gpr[a->rt + 1];
102 hi = cpu_gpr[a->rt];
107 tcg_gen_concat_i64_i128(t16, lo, hi);
111 tcg_gen_extr_i128_i64(lo, hi, t16);
655 TCGv_i64 hi = tcg_temp_new_i64();
658 tcg_gen_muls2_i64(lo, hi, cpu_gpr[a->vra], cpu_gpr[a->vrb]);
660 tcg_gen_add2_i64(t1, cpu_gpr[a->vrt], lo, hi, cpu_gpr[a->rc], t1);
673 TCGv_i64 hi = tcg_temp_new_i64();
676 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[a->vra], cpu_gpr[a->vrb]);
[all …]
/qemu/linux-user/mips/
H A Dsignal.c116 __put_user(regs->active_tc.HI[0], &sc->sc_mdhi); in setup_sigcontext()
121 __put_user(regs->active_tc.HI[1], &sc->sc_hi1); in setup_sigcontext()
122 __put_user(regs->active_tc.HI[2], &sc->sc_hi2); in setup_sigcontext()
123 __put_user(regs->active_tc.HI[3], &sc->sc_hi3); in setup_sigcontext()
146 __get_user(regs->active_tc.HI[0], &sc->sc_mdhi); in restore_sigcontext()
153 __get_user(regs->active_tc.HI[1], &sc->sc_hi1); in restore_sigcontext()
154 __get_user(regs->active_tc.HI[2], &sc->sc_hi2); in restore_sigcontext()
155 __get_user(regs->active_tc.HI[3], &sc->sc_hi3); in restore_sigcontext()
/qemu/tests/tcg/ppc64/
H A Dxxspltw.c14 #define TEST(HI, LO, UIM, RES) \ argument
19 } h = { .u = HI }, l = { .u = LO }; \
33 " %016" PRIx64 "%016" PRIx64 "\n", HI, LO, UIM, \
/qemu/hw/dma/
H A Dsoc_dma.c112 int hi; in soc_dma_lookup() local
115 hi = dma->memmap_size; in soc_dma_lookup()
117 while (hi > 1) { in soc_dma_lookup()
118 hi /= 2; in soc_dma_lookup()
119 if (lo[hi].addr <= addr) in soc_dma_lookup()
120 lo += hi; in soc_dma_lookup()
/qemu/tests/qtest/libqos/
H A Dvirtio-pci-modern.c43 uint64_t lo, hi; in get_features() local
56 hi = qpci_io_readl(dev->pdev, dev->bar, dev->common_cfg_offset + in get_features()
59 return (hi << 32) | lo; in get_features()
90 uint64_t lo, hi; in get_guest_features() local
103 hi = qpci_io_readl(dev->pdev, dev->bar, dev->common_cfg_offset + in get_guest_features()
106 return (hi << 32) | lo; in get_guest_features()
H A Dvirtio-mmio.c47 uint64_t hi = 0; in qvirtio_mmio_get_features() local
54 hi = qtest_readl(dev->qts, dev->addr + QVIRTIO_MMIO_HOST_FEATURES); in qvirtio_mmio_get_features()
57 return (hi << 32) | lo; in qvirtio_mmio_get_features()
/qemu/tcg/
H A Dtcg-op-ldst.c546 TCGv_i64 lo, hi; in tcg_gen_qemu_ld_i128_int() local
552 hi = TCGV128_LOW(val); in tcg_gen_qemu_ld_i128_int()
557 hi = TCGV128_HIGH(val); in tcg_gen_qemu_ld_i128_int()
561 tcgv_i64_temp(hi), addr, oi); in tcg_gen_qemu_ld_i128_int()
565 tcg_gen_bswap64_i64(hi, hi); in tcg_gen_qemu_ld_i128_int()
653 TCGv_i64 lo, hi; in tcg_gen_qemu_st_i128_int() local
659 hi = tcg_temp_ebb_new_i64(); in tcg_gen_qemu_st_i128_int()
661 tcg_gen_bswap64_i64(hi, TCGV128_LOW(val)); in tcg_gen_qemu_st_i128_int()
666 hi = TCGV128_HIGH(val); in tcg_gen_qemu_st_i128_int()
670 tcgv_i64_temp(lo), tcgv_i64_temp(hi), addr, oi); in tcg_gen_qemu_st_i128_int()
[all …]
/qemu/
H A D.patchew.yml85 Hi,
92 Hi,
102 Hi,

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