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/linux-5.10/drivers/gpu/drm/i915/gt/
Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
17 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
21 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
22 * produced by non-pipelined state commands), software needs to first
23 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
24 * 0.
26 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
27 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
31 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
32 * BEFORE the pipe-control with a post-sync op and no write-cache
[all …]
Dgen2_engine_cs.c1 // SPDX-License-Identifier: MIT
17 u32 cmd, *cs; in gen2_emit_flush() local
23 cs = intel_ring_begin(rq, 2 + 4 * num_store_dw); in gen2_emit_flush()
24 if (IS_ERR(cs)) in gen2_emit_flush()
25 return PTR_ERR(cs); in gen2_emit_flush()
27 *cs++ = cmd; in gen2_emit_flush()
28 while (num_store_dw--) { in gen2_emit_flush()
29 *cs++ = MI_STORE_DWORD_INDEX; in gen2_emit_flush()
30 *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); in gen2_emit_flush()
31 *cs++ = 0; in gen2_emit_flush()
[all …]
Dgen7_renderclear.c1 // SPDX-License-Identifier: MIT
12 #define GT3_INLINE_DATA_DELAYS 0x1E00
13 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) argument
53 bv->max_primitives = 280; in batch_get_defaults()
54 bv->max_urb_entries = MAX_URB_ENTRIES; in batch_get_defaults()
55 bv->surface_height = 16 * 16; in batch_get_defaults()
56 bv->surface_width = 32 * 2 * 16; in batch_get_defaults()
58 bv->max_primitives = 128; in batch_get_defaults()
59 bv->max_urb_entries = MAX_URB_ENTRIES / 2; in batch_get_defaults()
60 bv->surface_height = 16 * 8; in batch_get_defaults()
[all …]
/linux-5.10/kernel/time/
Dclocksource.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include "tick-internal.h"
22 * clocks_calc_mult_shift - calculate mult/shift factors for scaled math of clocks
57 sftacc--; in clocks_calc_mult_shift()
64 for (sft = 32; sft > 0; sft--) { in clocks_calc_mult_shift()
68 if ((tmp >> sftacc) == 0) in clocks_calc_mult_shift()
76 /*[Clocksource internal variables]---------
86 * Name of the user-specified clocksource.
119 static void __clocksource_change_rating(struct clocksource *cs, int rating);
145 static void __clocksource_unstable(struct clocksource *cs) in __clocksource_unstable() argument
[all …]
/linux-5.10/drivers/scsi/
Dmyrs.c1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
52 for (i = 0; i < ARRAY_SIZE(myrs_devstate_name_list); i++) { in myrs_devstate_name()
83 for (i = 0; i < ARRAY_SIZE(myrs_raid_level_name_list); i++) { in myrs_raid_level_name()
91 * myrs_reset_cmd - clears critical fields in struct myrs_cmdblk
95 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_reset_cmd()
97 memset(mbox, 0, sizeof(union myrs_cmd_mbox)); in myrs_reset_cmd()
98 cmd_blk->status = 0; in myrs_reset_cmd()
102 * myrs_qcmd - queues Command for DAC960 V2 Series Controllers.
[all …]
/linux-5.10/drivers/memory/
Dstm32-fmc2-ebi.c1 // SPDX-License-Identifier: GPL-2.0
16 #define FMC2_BCR1 0x0
17 #define FMC2_BTR1 0x4
18 #define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1)
19 #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1)
20 #define FMC2_PCSCNTR 0x20
21 #define FMC2_BWTR1 0x104
22 #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1)
29 #define FMC2_BCR_MBKEN BIT(0)
46 #define FMC2_BXTR_ADDSET GENMASK(3, 0)
[all …]
Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
30 #include <linux/omap-gpmc.h>
34 #include <linux/platform_data/mtd-nand-omap2.h>
36 #define DEVICE_NAME "omap-gpmc"
39 #define GPMC_REVISION 0x00
40 #define GPMC_SYSCONFIG 0x10
41 #define GPMC_SYSSTATUS 0x14
42 #define GPMC_IRQSTATUS 0x18
[all …]
/linux-5.10/drivers/misc/habanalabs/common/
Dcommand_submission.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
25 struct hl_device *hdev = hw_sob->hdev; in hl_sob_reset()
27 hdev->asic_funcs->reset_sob(hdev, hw_sob); in hl_sob_reset()
34 struct hl_device *hdev = hw_sob->hdev; in hl_sob_reset_error()
36 dev_crit(hdev->dev, in hl_sob_reset_error()
38 hw_sob->q_idx, hw_sob->sob_id); in hl_sob_reset_error()
47 struct hl_device *hdev = hl_cs_cmpl->hdev; in hl_fence_release()
49 /* EBUSY means the CS was never submitted and hence we don't have in hl_fence_release()
52 if (fence->error == -EBUSY) in hl_fence_release()
[all …]
/linux-5.10/drivers/mfd/
Datmel-smc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
18 * Set all fields to 0 so that one can start defining a new config.
22 memset(conf, 0, sizeof(*conf)); in atmel_smc_cs_conf_init()
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
40 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
41 * the encodedval is contains the maximum val. Otherwise, 0 is returned.
[all …]
/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
[all …]
Dst,stm32-fmc2-ebi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
22 - Christophe Kerello <christophe.kerello@st.com>
26 const: st,stm32mp1-fmc2-ebi
37 "#address-cells":
[all …]
/linux-5.10/arch/m68k/include/asm/
Dm5307sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
27 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */
28 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
29 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
30 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
31 #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
32 #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */
33 #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */
34 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
[all …]
Dm5407sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5407sim.h -- ColdFire 5407 System Integration Module support.
27 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
28 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
29 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
30 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
31 #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
32 #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
33 #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */
34 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
[all …]
/linux-5.10/include/linux/mfd/syscon/
Datmel-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
[all …]
/linux-5.10/kernel/cgroup/
Dcpuset.c7 * Copyright (C) 2004-2007 Silicon Graphics, Inc.
11 * sysfs is Copyright (c) 2001-3 Patrick Mochel
13 * 2003-10-10 Written by Simon Derr.
14 * 2003-10-22 Updates by Stephen Hemminger.
15 * 2004 May-July Rework by Paul Jackson.
59 #include <linux/backing-dev.h>
89 * The user-configured masks can only be changed by writing to
103 * The user-configured masks are always the same with effective masks.
106 /* user-configured CPUs and Memory Nodes allow to tasks */
115 * CPUs allocated to child sub-partitions (default hierarchy only)
[all …]
/linux-5.10/fs/fuse/
Ddev.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
29 #define FUSE_INT_REQ_BIT (1ULL << 0)
37 * Lockless access is OK, because file->private data is set in fuse_get_dev()
40 return READ_ONCE(file->private_data); in fuse_get_dev()
45 INIT_LIST_HEAD(&req->list); in fuse_request_init()
46 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
47 init_waitqueue_head(&req->waitq); in fuse_request_init()
48 refcount_set(&req->count, 1); in fuse_request_init()
49 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
50 req->fm = fm; in fuse_request_init()
[all …]
/linux-5.10/arch/mips/bcm63xx/
Dcs.c24 static int is_valid_cs(unsigned int cs) in is_valid_cs() argument
26 if (cs > 6) in is_valid_cs()
27 return 0; in is_valid_cs()
35 int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size) in bcm63xx_set_cs_base() argument
40 if (!is_valid_cs(cs)) in bcm63xx_set_cs_base()
41 return -EINVAL; in bcm63xx_set_cs_base()
45 return -EINVAL; in bcm63xx_set_cs_base()
48 return -EINVAL; in bcm63xx_set_cs_base()
51 /* 8k => 0 - 256M => 15 */ in bcm63xx_set_cs_base()
52 val |= (ilog2(size) - ilog2(8 * 1024)) << MPI_CSBASE_SIZE_SHIFT; in bcm63xx_set_cs_base()
[all …]
/linux-5.10/net/ceph/
Dstring_table.c1 // SPDX-License-Identifier: GPL-2.0
13 struct ceph_string *cs, *exist; in ceph_find_or_create_string() local
23 if (ret > 0) in ceph_find_or_create_string()
24 p = &(*p)->rb_left; in ceph_find_or_create_string()
25 else if (ret < 0) in ceph_find_or_create_string()
26 p = &(*p)->rb_right; in ceph_find_or_create_string()
31 if (exist && !kref_get_unless_zero(&exist->kref)) { in ceph_find_or_create_string()
32 rb_erase(&exist->node, &string_tree); in ceph_find_or_create_string()
33 RB_CLEAR_NODE(&exist->node); in ceph_find_or_create_string()
40 cs = kmalloc(sizeof(*cs) + len + 1, GFP_NOFS); in ceph_find_or_create_string()
[all …]
/linux-5.10/drivers/clocksource/
Dtimer-pistachio.c2 * Pistachio clocksource based on general-purpose timers
29 #define CR_TIMER_CTRL_CFG 0x00
30 #define TIMER_ME_GLOBAL BIT(0)
31 #define CR_TIMER_REV 0x10
34 #define TIMER_CFG 0x20
35 #define TIMER_ME_LOCAL BIT(0)
36 #define TIMER_RELOAD_VALUE 0x24
37 #define TIMER_CURRENT_VALUE 0x28
38 #define TIMER_CURRENT_OVERFLOW_VALUE 0x2C
39 #define TIMER_IRQ_STATUS 0x30
[all …]
/linux-5.10/drivers/staging/kpc2000/
Dkpc2000_spi.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2014-2018 Daktronics
7 * Very loosely based on spi-omap2-mcspi.c
13 #include <linux/io-64-nonatomic-lo-hi.h>
33 { .name = "SLOT_0", .size = 7798784, .offset = 0, },
41 { .name = "SLOT_4", .size = 7798784, .offset = 0, },
64 .chip_select = 0,
80 #define KP_SPI_REG_CONFIG 0x0 /* 0x00 */
81 #define KP_SPI_REG_STATUS 0x1 /* 0x08 */
82 #define KP_SPI_REG_FFCTRL 0x2 /* 0x10 */
[all …]
/linux-5.10/drivers/spi/
Dspi-fsl-spi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <linux/dma-mapping.h>
42 #define IMMR_SPI_CS_OFFSET 0x14c
43 #define SPI_BOOT_SEL_BIT 0x80000000
45 #include "spi-fsl-lib.h"
46 #include "spi-fsl-cpm.h"
47 #include "spi-fsl-spi.h"
49 #define TYPE_FSL 0
81 if (dev->of_node) { in fsl_spi_get_type()
82 match = of_match_node(of_fsl_spi_match, dev->of_node); in fsl_spi_get_type()
[all …]
/linux-5.10/tools/perf/util/
Dcomm.c1 // SPDX-License-Identifier: GPL-2.0
22 static struct comm_str *comm_str__get(struct comm_str *cs) in comm_str__get() argument
24 if (cs && refcount_inc_not_zero(&cs->refcnt)) in comm_str__get()
25 return cs; in comm_str__get()
30 static void comm_str__put(struct comm_str *cs) in comm_str__put() argument
32 if (cs && refcount_dec_and_test(&cs->refcnt)) { in comm_str__put()
34 rb_erase(&cs->rb_node, &comm_str_root); in comm_str__put()
36 zfree(&cs->str); in comm_str__put()
37 free(cs); in comm_str__put()
43 struct comm_str *cs; in comm_str__alloc() local
[all …]
/linux-5.10/arch/mips/include/asm/netlogic/xlr/
Dflash.h2 * Copyright (c) 2003-2012 Broadcom Corporation
37 #define FLASH_CSBASE_ADDR(cs) (cs) argument
38 #define FLASH_CSADDR_MASK(cs) (0x10 + (cs)) argument
39 #define FLASH_CSDEV_PARM(cs) (0x20 + (cs)) argument
40 #define FLASH_CSTIME_PARMA(cs) (0x30 + (cs)) argument
41 #define FLASH_CSTIME_PARMB(cs) (0x40 + (cs)) argument
43 #define FLASH_INT_MASK 0x50
44 #define FLASH_INT_STATUS 0x60
45 #define FLASH_ERROR_STATUS 0x70
46 #define FLASH_ERROR_ADDR 0x80
[all …]
/linux-5.10/drivers/gpu/drm/i915/selftests/
Di915_perf.c2 * SPDX-License-Identifier: MIT
17 #define TEST_OA_CONFIG_UUID "12345678-1234-1234-1234-1234567890ab"
26 return -ENOMEM; in alloc_empty_config()
28 oa_config->perf = perf; in alloc_empty_config()
29 kref_init(&oa_config->ref); in alloc_empty_config()
31 strlcpy(oa_config->uuid, TEST_OA_CONFIG_UUID, sizeof(oa_config->uuid)); in alloc_empty_config()
33 mutex_lock(&perf->metrics_lock); in alloc_empty_config()
35 oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL); in alloc_empty_config()
36 if (oa_config->id < 0) { in alloc_empty_config()
37 mutex_unlock(&perf->metrics_lock); in alloc_empty_config()
[all …]
/linux-5.10/drivers/s390/char/
Draw3270.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 #define TC_WRITE 0x01 /* Write */
24 #define TC_RDBUF 0x02 /* Read Buffer */
25 #define TC_EWRITE 0x05 /* Erase write */
26 #define TC_READMOD 0x06 /* Read modified */
27 #define TC_EWRITEA 0x0d /* Erase write alternate */
28 #define TC_WRITESF 0x11 /* Write structured field */
31 #define TO_SF 0x1d /* Start field */
32 #define TO_SBA 0x11 /* Set buffer address */
33 #define TO_IC 0x13 /* Insert cursor */
[all …]

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