2  * Pistachio clocksource based on general-purpose timers
29 #define CR_TIMER_CTRL_CFG		0x00
30 #define TIMER_ME_GLOBAL			BIT(0)
31 #define CR_TIMER_REV			0x10
34 #define TIMER_CFG			0x20
35 #define TIMER_ME_LOCAL			BIT(0)
36 #define TIMER_RELOAD_VALUE		0x24
37 #define TIMER_CURRENT_VALUE		0x28
38 #define TIMER_CURRENT_OVERFLOW_VALUE	0x2C
39 #define TIMER_IRQ_STATUS		0x30
40 #define TIMER_IRQ_CLEAR			0x34
41 #define TIMER_IRQ_MASK			0x38
43 #define PERIP_TIMER_CONTROL		0x90
46 #define RELOAD_VALUE			0xffffffff
51 	struct clocksource cs;  member
56 #define to_pistachio_clocksource(cs)	\  argument
57 	container_of(cs, struct pistachio_clocksource, cs)
61 	return readl(base + 0x20 * gpt_id + offset);  in gpt_readl()
67 	writel(value, base + 0x20 * gpt_id + offset);  in gpt_writel()
71 pistachio_clocksource_read_cycles(struct clocksource *cs)  in pistachio_clocksource_read_cycles()  argument
73 	struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);  in pistachio_clocksource_read_cycles()
82 	raw_spin_lock_irqsave(&pcs->lock, flags);  in pistachio_clocksource_read_cycles()
83 	overflw = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0);  in pistachio_clocksource_read_cycles()
84 	counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0);  in pistachio_clocksource_read_cycles()
85 	raw_spin_unlock_irqrestore(&pcs->lock, flags);  in pistachio_clocksource_read_cycles()
92 	return pistachio_clocksource_read_cycles(&pcs_gpt.cs);  in pistachio_read_sched_clock()
95 static void pistachio_clksrc_set_mode(struct clocksource *cs, int timeridx,  in pistachio_clksrc_set_mode()  argument
98 	struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);  in pistachio_clksrc_set_mode()
101 	val = gpt_readl(pcs->base, TIMER_CFG, timeridx);  in pistachio_clksrc_set_mode()
107 	gpt_writel(pcs->base, val, TIMER_CFG, timeridx);  in pistachio_clksrc_set_mode()
110 static void pistachio_clksrc_enable(struct clocksource *cs, int timeridx)  in pistachio_clksrc_enable()  argument
112 	struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);  in pistachio_clksrc_enable()
115 	pistachio_clksrc_set_mode(cs, timeridx, false);  in pistachio_clksrc_enable()
116 	gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx);  in pistachio_clksrc_enable()
117 	pistachio_clksrc_set_mode(cs, timeridx, true);  in pistachio_clksrc_enable()
120 static void pistachio_clksrc_disable(struct clocksource *cs, int timeridx)  in pistachio_clksrc_disable()  argument
123 	pistachio_clksrc_set_mode(cs, timeridx, false);  in pistachio_clksrc_disable()
126 static int pistachio_clocksource_enable(struct clocksource *cs)  in pistachio_clocksource_enable()  argument
128 	pistachio_clksrc_enable(cs, 0);  in pistachio_clocksource_enable()
129 	return 0;  in pistachio_clocksource_enable()
132 static void pistachio_clocksource_disable(struct clocksource *cs)  in pistachio_clocksource_disable()  argument
134 	pistachio_clksrc_disable(cs, 0);  in pistachio_clocksource_disable()
139 	.cs =	{
158 	pcs_gpt.base = of_iomap(node, 0);  in pistachio_clksrc_of_init()
161 		return -ENXIO;  in pistachio_clksrc_of_init()
164 	periph_regs = syscon_regmap_lookup_by_phandle(node, "img,cr-periph");  in pistachio_clksrc_of_init()
173 				 0xf, 0x0);  in pistachio_clksrc_of_init()
190 	if (ret < 0) {  in pistachio_clksrc_of_init()
196 	if (ret < 0) {  in pistachio_clksrc_of_init()
205 	gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 0);  in pistachio_clksrc_of_init()
206 	gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 1);  in pistachio_clksrc_of_init()
207 	gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 2);  in pistachio_clksrc_of_init()
208 	gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 3);  in pistachio_clksrc_of_init()
215 	return clocksource_register_hz(&pcs_gpt.cs, rate);  in pistachio_clksrc_of_init()
217 TIMER_OF_DECLARE(pistachio_gptimer, "img,pistachio-gptimer",