| /qemu/hw/intc/ |
| H A D | riscv_imsic.c | 92 target_ulong new_val, in riscv_imsic_eidelivery_rmw()
110 target_ulong new_val, in riscv_imsic_eithreshold_rmw()
127 target_ulong *val, target_ulong new_val, in riscv_imsic_topei_rmw()
153 target_ulong new_val, target_ulong wr_mask) in riscv_imsic_eix_rmw()
201 target_ulong new_val, target_ulong wr_mask) in riscv_imsic_rmw()
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| /qemu/target/riscv/ |
| H A D | csr.c | 1432 target_ulong *val, target_ulong new_val, in rmw_cd_mhpmcounter()
1451 target_ulong *val, target_ulong new_val, in rmw_cd_mhpmcounterh()
1470 target_ulong *val, target_ulong new_val, in rmw_cd_mhpmevent()
1502 target_ulong *val, target_ulong new_val, in rmw_cd_mhpmeventh()
1532 target_ulong new_val, target_ulong wr_mask) in rmw_cd_ctr_cfg()
1559 target_ulong new_val, target_ulong wr_mask) in rmw_cd_ctr_cfgh()
2192 uint64_t new_val, uint64_t wr_mask) in rmw_mideleg64()
2211 target_ulong new_val, target_ulong wr_mask) in rmw_mideleg()
2226 target_ulong new_val, in rmw_midelegh()
2243 uint64_t new_val, uint64_t wr_mask) in rmw_mie64()
[all …]
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| H A D | debug.c | 531 target_ulong new_val; in type2_reg_write() local
645 target_ulong new_val; in type6_reg_write() local
821 target_ulong new_val; in itrigger_reg_write() local
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| H A D | cpu_helper.c | 773 target_ulong new_val, in riscv_cpu_set_aia_ireg_rmw_fn()
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| /qemu/hw/remote/ |
| H A D | proxy.c | 294 uint32_t orig_val, new_val, base_class, val; in probe_pci_info() local
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| /qemu/hw/misc/ |
| H A D | xlnx-versal-crl.c | 77 #define REGFIELD_RESET(type, s, reg, f, new_val, dev) { \ argument
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| /qemu/hw/display/ |
| H A D | jazz_led.c | 66 uint8_t new_val = val & 0xff; in jazz_led_write() local
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| /qemu/hw/core/ |
| H A D | register.c | 74 uint64_t old_val, new_val, test, no_w_mask; in register_write() local
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| H A D | qdev-properties-system.c | 41 const void *old_val, const char *new_val, in check_prop_still_unset()
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| /qemu/rust/hw/timer/hpet/src/ |
| H A D | device.rs | 407 let mut new_val: u64 = old_val.deposit(shift, len, val); in set_tn_cfg_reg() localVariable
629 let mut new_val = old_val.deposit(shift, len, val); set_cfg_reg() localVariable
671 let new_val = val << shift; set_int_status_reg() localVariable
[all...] |
| /qemu/hw/timer/ |
| H A D | exynos4210_pwm.c | 275 uint32_t new_val; in exynos4210_pwm_write() local
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| H A D | hpet.c | 483 uint64_t old_val, new_val, cleared; in hpet_ram_write() local
[all...] |
| /qemu/tcg/ |
| H A D | tcg-op-ldst.c | 1108 TCGArg idx, MemOp memop, bool new_val, in do_nonatomic_op_i32()
1149 TCGArg idx, MemOp memop, bool new_val, in do_nonatomic_op_i64()
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| /qemu/hw/net/ |
| H A D | tulip.c | 712 uint32_t new_val) in tulip_csr9_write()
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| /qemu/rust/hw/char/pl011/src/ |
| H A D | device.rs | 241 let new_val: registers::LineControl = value.into(); in write() localVariable
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| /qemu/hw/ssi/ |
| H A D | xlnx-versal-ospi.c | 1248 static bool ind_wr_clearing_op_done(XlnxVersalOspi *s, uint64_t new_val) in ind_wr_clearing_op_done()
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| /qemu/hw/xen/ |
| H A D | xen_pt_config_init.c | 1971 uint32_t new_val; in xen_pt_config_reg_init() local
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| /qemu/hw/i386/ |
| H A D | intel_iommu.c | 173 uint32_t new_val = (ldl_le_p(&s->csr[addr]) & ~clear) | mask; in vtd_set_clear_mask_long() local
181 uint64_t new_val = (ldq_le_p(&s->csr[addr]) & ~clear) | mask; in vtd_set_clear_mask_quad() local
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| /qemu/target/arm/ |
| H A D | ptw.c | 737 uint64_t new_val, S1Translate *ptw, in arm_casq_ptw()
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| /qemu/target/hexagon/ |
| H A D | genptr.c | 59 static inline void gen_masked_reg_write(TCGv new_val, TCGv cur_val, in gen_masked_reg_write()
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