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Searched refs:tmp2 (Results 1 – 16 of 16) sorted by relevance

/qemu/util/
H A Dinterval-tree.c351 RBNode *node = NULL, *sibling, *tmp1, *tmp2; in rb_erase_color() local
383 tmp2 = sibling->rb_left; in rb_erase_color()
384 if (!tmp2 || rb_is_black(tmp2)) { in rb_erase_color()
439 tmp1 = tmp2->rb_right; in rb_erase_color()
441 qatomic_set(&tmp2->rb_right, sibling); in rb_erase_color()
442 qatomic_set(&parent->rb_right, tmp2); in rb_erase_color()
446 augment->rotate(sibling, tmp2); in rb_erase_color()
448 sibling = tmp2; in rb_erase_color()
462 tmp2 = sibling->rb_left; in rb_erase_color()
463 qatomic_set(&parent->rb_right, tmp2); in rb_erase_color()
[all …]
/qemu/tests/tcg/aarch64/system/
H A Dmte.S15 #define tmp2 x4 /* Scratch register. */ macro
59 mrs tmp2, sctlr_el1
61 orr tmp2, tmp2, tmp3
62 msr sctlr_el1, tmp2
/qemu/docs/spin/
H A Dwin32-qemu-event.promela56 int tmp1, tmp2;
61 atomic { /* tmp2=cas(state, EV_FREE, EV_BUSY) */ \
62 tmp2 = state; \
63 if :: tmp2 == EV_FREE -> state = EV_BUSY; \
67 if :: tmp2 == EV_SET -> tmp1 = EV_SET; \
/qemu/target/mips/tcg/
H A Dop_helper.c77 uint64_t tmp2 = tmp1; in helper_rotx() local
88 tmp2 |= 1LL << i; in helper_rotx()
90 tmp2 &= ~(1LL << i); in helper_rotx()
95 uint64_t tmp3 = tmp2; in helper_rotx()
104 if (tmp2 & (1LL << (i + 4))) { in helper_rotx()
H A Dnanomips_translate.c.inc998 TCGv tmp2 = tcg_temp_new();
1004 tcg_gen_extr_i64_tl(tmp2, tmp1, tval);
1006 tcg_gen_extr_i64_tl(tmp1, tmp2, tval);
1009 gen_store_gpr(tmp2, reg2);
1023 TCGv tmp2 = tcg_temp_new();
1033 gen_load_gpr(tmp2, reg2);
1036 tcg_gen_concat_tl_i64(tval, tmp2, tmp1);
1038 tcg_gen_concat_tl_i64(tval, tmp1, tmp2);
/qemu/target/arm/tcg/
H A Dtranslate.c412 TCGv_i32 tmp2 = tcg_temp_new_i32(); in gen_smul_dual() local
414 tcg_gen_ext16s_i32(tmp2, b); in gen_smul_dual()
415 tcg_gen_mul_i32(tmp1, tmp1, tmp2); in gen_smul_dual()
1479 TCGv_i32 tmp, tmp2, tmp3; in disas_iwmmxt_insn() local
1588 tmp2 = load_reg(s, rd); in disas_iwmmxt_insn()
1589 tcg_gen_andc_i32(tmp, tmp, tmp2); in disas_iwmmxt_insn()
1814 tmp2 = tcg_constant_i32(0xff); in disas_iwmmxt_insn()
1818 tmp2 = tcg_constant_i32(0xffff); in disas_iwmmxt_insn()
1822 tmp2 = tcg_constant_i32(0xffffffff); in disas_iwmmxt_insn()
1828 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3); in disas_iwmmxt_insn()
[all …]
H A Dtranslate-neon.c2790 TCGv_i32 ahp, tmp, tmp2, tmp3; in trans_VCVT_F16_F32() local
2816 tmp2 = tcg_temp_new_i32(); in trans_VCVT_F16_F32()
2817 read_neon_element32(tmp2, a->vm, 1, MO_32); in trans_VCVT_F16_F32()
2818 gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp); in trans_VCVT_F16_F32()
2819 tcg_gen_shli_i32(tmp2, tmp2, 16); in trans_VCVT_F16_F32()
2820 tcg_gen_or_i32(tmp2, tmp2, tmp); in trans_VCVT_F16_F32()
2825 write_neon_element32(tmp2, a->vd, 0, MO_32); in trans_VCVT_F16_F32()
2836 TCGv_i32 ahp, tmp, tmp2, tmp3; in trans_VCVT_F32_F16() local
2860 tmp2 = tcg_temp_new_i32(); in trans_VCVT_F32_F16()
2863 read_neon_element32(tmp2, a->vm, 1, MO_32); in trans_VCVT_F32_F16()
[all …]
H A Dneon_helper.c837 uint64_t tmp1, tmp2; in HELPER() local
846 tmp2 = (a >> 8) & elementmask; in HELPER()
847 tmp2 ^= nsignmask; in HELPER()
848 tmp2 |= wsignmask; in HELPER()
849 tmp2 = (tmp2 - nsignmask) ^ wsignmask; in HELPER()
855 signres = (tmp1 ^ tmp2) & wsignmask; in HELPER()
856 res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask); in HELPER()
/qemu/target/alpha/
H A Dtranslate.c270 TCGv_i32 tmp1, tmp2; in gen_excp_1() local
273 tmp2 = tcg_constant_i32(error_code); in gen_excp_1()
274 gen_helper_excp(tcg_env, tmp1, tmp2); in gen_excp_1()
1373 TCGv va, vb, vc, tmp, tmp2; in translate_one() local
1605 tmp2 = tcg_temp_new(); in translate_one()
1607 tcg_gen_mov_i64(tmp2, va); in translate_one()
1609 tcg_gen_xor_i64(tmp2, tmp2, vc); in translate_one()
1610 tcg_gen_and_i64(tmp, tmp, tmp2); in translate_one()
1612 tcg_gen_movi_i64(tmp2, 0); in translate_one()
1613 gen_helper_check_overflow(tcg_env, tmp, tmp2); in translate_one()
[all …]
/qemu/tests/tcg/alpha/system/
H A Dboot.S226 #define tmp2 $4 macro
243 2: addq quotient, mask, tmp2
247 cmovne compare, tmp2, quotient
264 #undef tmp2
/qemu/tests/qemu-iotests/
H A D144.out50 'snapshot-file':'TEST_DIR/tmp2.IMGFMT',
54 Formatting 'TEST_DIR/tmp2.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zli…
H A D14433 TMP_SNAP2=${TEST_DIR}/tmp2.qcow2
/qemu/target/riscv/insn_trans/
H A Dtrans_xthead.c.inc491 TCGv tmp2 = tcg_temp_new();
493 extend_operand_func(tmp2, src2);
494 tcg_gen_mul_tl(tmp, tmp, tmp2);
/qemu/target/hexagon/idef-parser/
H A Dparser-helpers.c780 HexValue tmp1, tmp2; in gen_andl_op() local
783 memset(&tmp2, 0, sizeof(HexValue)); in gen_andl_op()
793 tmp2 = gen_bin_cmp(c, locp, TCG_COND_NE, op2, &zero); in gen_andl_op()
795 "(", res, ", ", &tmp1, ", ", &tmp2, ");\n"); in gen_andl_op()
/qemu/target/xtensa/
H A Dtranslate.c1437 TCGv_i32 tmp2 = tcg_temp_new_i32(); in translate_boolean() local
1440 tcg_gen_shri_i32(tmp2, arg[2].in, arg[2].imm); in translate_boolean()
1441 op[par[0]](tmp1, tmp1, tmp2); in translate_boolean()
1490 TCGv_i32 tmp2 = tcg_constant_i32((1 << arg[2].imm) - 1); in translate_clamps() local
1493 tcg_gen_smin_i32(arg[0].out, arg[0].out, tmp2); in translate_clamps()
6519 TCGv_i64 tmp2 = tcg_temp_new_i64(); in translate_movp_d() local
6522 tcg_gen_extu_i32_i64(tmp2, tmp1); in translate_movp_d()
6524 arg[0].out, tmp2, zero, in translate_movp_d()
/qemu/target/m68k/
H A Dtranslate.c1184 TCGv tmp, tmp2; in gen_cc_cond() local
1340 tmp2 = tcg_temp_new(); in gen_cc_cond()
1341 tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V); in gen_cc_cond()
1342 tcg_gen_or_i32(tmp, tmp, tmp2); in gen_cc_cond()