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Searched refs:tmp1 (Results 1 – 17 of 17) sorted by relevance

/qemu/tests/tcg/aarch64/system/
H A Dmte.S14 #define tmp1 x3 /* Scratch register. */ macro
45 mrs tmp1, tcr_el1
46 orr tmp1, tmp1, (1 << 37)
47 msr tcr_el1, tmp1
104 ldr tmp1, =0xdeadbeef
105 str tmp1, [tagged_addr]
/qemu/util/
H A Dinterval-tree.c351 RBNode *node = NULL, *sibling, *tmp1, *tmp2; in rb_erase_color() local
373 tmp1 = sibling->rb_left; in rb_erase_color()
374 qatomic_set(&parent->rb_right, tmp1); in rb_erase_color()
376 rb_set_parent_color(tmp1, parent, RB_BLACK); in rb_erase_color()
379 sibling = tmp1; in rb_erase_color()
381 tmp1 = sibling->rb_right; in rb_erase_color()
382 if (!tmp1 || rb_is_black(tmp1)) { in rb_erase_color()
439 tmp1 = tmp2->rb_right; in rb_erase_color()
440 qatomic_set(&sibling->rb_left, tmp1); in rb_erase_color()
443 if (tmp1) { in rb_erase_color()
[all …]
/qemu/docs/spin/
H A Dwin32-qemu-event.promela56 int tmp1, tmp2;
57 #define WAIT tmp1 = state; \
58 if :: tmp1 != EV_SET -> \
59 if :: tmp1 == EV_FREE -> \
67 if :: tmp2 == EV_SET -> tmp1 = EV_SET; \
68 :: else -> tmp1 = EV_BUSY; \
72 assert(tmp1 != EV_FREE); \
73 if :: tmp1 == EV_BUSY -> RAW_WAIT; \
/qemu/target/mips/tcg/
H A Dop_helper.c56 uint64_t tmp1 = tmp0; in helper_rotx() local
70 tmp1 |= 1LL << i; in helper_rotx()
72 tmp1 &= ~(1LL << i); in helper_rotx()
77 uint64_t tmp2 = tmp1; in helper_rotx()
87 if (tmp1 & (1LL << (i + 8))) { in helper_rotx()
H A Dnanomips_translate.c.inc997 TCGv tmp1 = tcg_temp_new();
1004 tcg_gen_extr_i64_tl(tmp2, tmp1, tval);
1006 tcg_gen_extr_i64_tl(tmp1, tmp2, tval);
1008 gen_store_gpr(tmp1, reg1);
1022 TCGv tmp1 = tcg_temp_new();
1032 gen_load_gpr(tmp1, reg1);
1036 tcg_gen_concat_tl_i64(tval, tmp2, tmp1);
1038 tcg_gen_concat_tl_i64(tval, tmp1, tmp2);
/qemu/target/rx/
H A Dop_helper.c201 uint8_t tmp0, tmp1; in helper_scmpu() local
207 tmp1 = cpu_ldub_data_ra(env, env->regs[2]++, GETPC()); in helper_scmpu()
209 if (tmp0 != tmp1 || tmp0 == '\0') { in helper_scmpu()
213 env->psw_z = tmp0 - tmp1; in helper_scmpu()
214 env->psw_c = (tmp0 >= tmp1); in helper_scmpu()
327 int64_t tmp0, tmp1; in helper_rmpa() local
340 tmp1 = cpu_ldfn[sz](env, env->regs[2], GETPC()); in helper_rmpa()
341 tmp0 *= tmp1; in helper_rmpa()
H A Dtranslate.c1703 TCGv_i64 tmp0, tmp1; in rx_mul64hi() local
1705 tmp1 = tcg_temp_new_i64(); in rx_mul64hi()
1708 tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); in rx_mul64hi()
1709 tcg_gen_sari_i64(tmp1, tmp1, 16); in rx_mul64hi()
1710 tcg_gen_mul_i64(ret, tmp0, tmp1); in rx_mul64hi()
1716 TCGv_i64 tmp0, tmp1; in rx_mul64lo() local
1718 tmp1 = tcg_temp_new_i64(); in rx_mul64lo()
1721 tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); in rx_mul64lo()
1722 tcg_gen_ext16s_i64(tmp1, tmp1); in rx_mul64lo()
1723 tcg_gen_mul_i64(ret, tmp0, tmp1); in rx_mul64lo()
/qemu/tests/tcg/alpha/system/
H A Dboot.S225 #define tmp1 $3 macro
246 subq modulus, divisor, tmp1
249 cmovne compare, tmp1, modulus
263 #undef tmp1
/qemu/target/arm/tcg/
H A Dtranslate.c411 TCGv_i32 tmp1 = tcg_temp_new_i32(); in gen_smul_dual() local
413 tcg_gen_ext16s_i32(tmp1, a); in gen_smul_dual()
415 tcg_gen_mul_i32(tmp1, tmp1, tmp2); in gen_smul_dual()
419 tcg_gen_mov_i32(a, tmp1); in gen_smul_dual()
533 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
535 tcg_gen_andi_i32(tmp1, t1, 0x1f); \
536 tcg_gen_##name##_i32(tmpd, t0, tmp1); \
537 tcg_gen_andi_i32(tmp1, t1, 0xe0); \
538 tcg_gen_movcond_i32(TCG_COND_NE, dest, tmp1, zero, zero, tmpd); \
546 TCGv_i32 tmp1 = tcg_temp_new_i32(); in GEN_SHIFT() local
[all …]
H A Dneon_helper.c837 uint64_t tmp1, tmp2; in HELPER() local
841 tmp1 = a & elementmask; in HELPER()
842 tmp1 ^= nsignmask; in HELPER()
843 tmp1 |= wsignmask; in HELPER()
844 tmp1 = (tmp1 - nsignmask) ^ wsignmask; in HELPER()
855 signres = (tmp1 ^ tmp2) & wsignmask; in HELPER()
856 res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask); in HELPER()
/qemu/bsd-user/
H A Delfload.c135 char *tmp, *tmp1, *pag = NULL; in copy_elf_strings() local
147 tmp1 = tmp; in copy_elf_strings()
151 len = tmp - tmp1; in copy_elf_strings()
/qemu/target/ppc/translate/
H A Dvmx-impl.c.inc2763 TCGv_i64 tmp0, tmp1, prod1h, prod1l, prod0h, prod0l, zero;
2769 tmp1 = tcg_temp_new_i64();
2778 get_avr64(tmp1, a->vrb, false);
2779 tcg_gen_mulu2_i64(prod1l, prod1h, tmp0, tmp1);
2783 get_avr64(tmp1, a->vrb, true);
2784 tcg_gen_mulu2_i64(prod0l, prod0h, tmp0, tmp1);
2787 get_avr64(tmp1, a->rc, false);
2788 tcg_gen_add2_i64(tmp1, tmp0, tmp1, zero, prod1l, zero);
2789 tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod0l, zero);
2795 get_avr64(tmp1, a->rc, true);
[all …]
/qemu/hw/s390x/
H A Dcss.c752 CCW1 tmp1; in copy_ccw_from_guest() local
756 cpu_physical_memory_read(addr, &tmp1, sizeof(tmp1)); in copy_ccw_from_guest()
757 ret.cmd_code = tmp1.cmd_code; in copy_ccw_from_guest()
758 ret.flags = tmp1.flags; in copy_ccw_from_guest()
759 ret.count = be16_to_cpu(tmp1.count); in copy_ccw_from_guest()
760 ret.cda = be32_to_cpu(tmp1.cda); in copy_ccw_from_guest()
/qemu/target/hexagon/idef-parser/
H A Dparser-helpers.c780 HexValue tmp1, tmp2; in gen_andl_op() local
782 memset(&tmp1, 0, sizeof(HexValue)); in gen_andl_op()
792 tmp1 = gen_bin_cmp(c, locp, TCG_COND_NE, op1, &zero); in gen_andl_op()
795 "(", res, ", ", &tmp1, ", ", &tmp2, ");\n"); in gen_andl_op()
/qemu/target/xtensa/
H A Dtranslate.c1436 TCGv_i32 tmp1 = tcg_temp_new_i32(); in translate_boolean() local
1439 tcg_gen_shri_i32(tmp1, arg[1].in, arg[1].imm); in translate_boolean()
1441 op[par[0]](tmp1, tmp1, tmp2); in translate_boolean()
1442 tcg_gen_deposit_i32(arg[0].out, arg[0].out, tmp1, arg[0].imm, 1); in translate_boolean()
1489 TCGv_i32 tmp1 = tcg_constant_i32(-1u << arg[2].imm); in translate_clamps() local
1492 tcg_gen_smax_i32(arg[0].out, tmp1, arg[1].in); in translate_clamps()
6518 TCGv_i32 tmp1 = tcg_temp_new_i32(); in translate_movp_d() local
6521 tcg_gen_andi_i32(tmp1, arg[2].in, 1 << arg[2].imm); in translate_movp_d()
6522 tcg_gen_extu_i32_i64(tmp2, tmp1); in translate_movp_d()
/qemu/target/alpha/
H A Dtranslate.c270 TCGv_i32 tmp1, tmp2; in gen_excp_1() local
272 tmp1 = tcg_constant_i32(exception); in gen_excp_1()
274 gen_helper_excp(tcg_env, tmp1, tmp2); in gen_excp_1()
/qemu/tcg/aarch64/
H A Dtcg-target.c.inc1671 /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {tmp0,tmp1}. */