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Searched refs:new_val (Results 1 – 24 of 24) sorted by relevance

/qemu/target/riscv/
H A Dcsr.c1432 target_ulong *val, target_ulong new_val, in rmw_cd_mhpmcounter() argument
1442 riscv_pmu_write_ctr(env, new_val, ctr_idx); in rmw_cd_mhpmcounter()
1451 target_ulong *val, target_ulong new_val, in rmw_cd_mhpmcounterh() argument
1461 riscv_pmu_write_ctrh(env, new_val, ctr_idx); in rmw_cd_mhpmcounterh()
1470 target_ulong *val, target_ulong new_val, in rmw_cd_mhpmevent() argument
1473 uint64_t mhpmevt_val = new_val; in rmw_cd_mhpmevent()
1486 mhpmevt_val = (new_val & wr_mask) | in rmw_cd_mhpmevent()
1502 target_ulong *val, target_ulong new_val, in rmw_cd_mhpmeventh() argument
1520 (new_val & wr_mask) | (env->mhpmeventh_val[evt_index] & ~wr_mask); in rmw_cd_mhpmeventh()
1532 target_ulong new_val, target_ulong wr_mask) in rmw_cd_ctr_cfg() argument
[all …]
H A Ddebug.c531 target_ulong new_val; in type2_reg_write() local
535 new_val = type2_mcontrol_validate(env, val); in type2_reg_write()
536 if (new_val != env->tdata1[index]) { in type2_reg_write()
537 env->tdata1[index] = new_val; in type2_reg_write()
645 target_ulong new_val; in type6_reg_write() local
649 new_val = type6_mcontrol6_validate(env, val); in type6_reg_write()
650 if (new_val != env->tdata1[index]) { in type6_reg_write()
651 env->tdata1[index] = new_val; in type6_reg_write()
821 target_ulong new_val; in itrigger_reg_write() local
826 new_val = itrigger_validate(env, val); in itrigger_reg_write()
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H A Dcpu.h463 target_ulong *val, target_ulong new_val, target_ulong write_mask);
635 target_ulong new_val,
H A Dcpu_helper.c773 target_ulong new_val, in riscv_cpu_set_aia_ireg_rmw_fn() argument
/qemu/hw/intc/
H A Driscv_imsic.c92 target_ulong new_val, in riscv_imsic_eidelivery_rmw() argument
102 imsic->eidelivery[page] = (old_val & ~wr_mask) | (new_val & wr_mask); in riscv_imsic_eidelivery_rmw()
110 target_ulong new_val, in riscv_imsic_eithreshold_rmw() argument
120 imsic->eithreshold[page] = (old_val & ~wr_mask) | (new_val & wr_mask); in riscv_imsic_eithreshold_rmw()
127 target_ulong *val, target_ulong new_val, in riscv_imsic_topei_rmw() argument
153 target_ulong new_val, target_ulong wr_mask) in riscv_imsic_eix_rmw() argument
183 if (new_val & mask) { in riscv_imsic_eix_rmw()
201 target_ulong new_val, target_ulong wr_mask) in riscv_imsic_rmw() argument
237 new_val, wr_mask); in riscv_imsic_rmw()
240 new_val, wr_mask); in riscv_imsic_rmw()
[all …]
/qemu/hw/timer/
H A Dhpet.c483 uint64_t old_val, new_val, cleared; in hpet_ram_write() local
495 new_val = deposit64(old_val, shift, len, value); in hpet_ram_write()
496 new_val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); in hpet_ram_write()
497 s->config = new_val; in hpet_ram_write()
498 if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) { in hpet_ram_write()
508 } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) { in hpet_ram_write()
517 if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) { in hpet_ram_write()
521 } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) { in hpet_ram_write()
528 new_val = value << shift; in hpet_ram_write()
529 cleared = new_val & s->isr; in hpet_ram_write()
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H A Dexynos4210_pwm.c275 uint32_t new_val; in exynos4210_pwm_write() local
340 new_val = (s->reg_tint_cstat & 0x3E0) + (0x1F & value); in exynos4210_pwm_write()
341 new_val &= ~(0x3E0 & value); in exynos4210_pwm_write()
344 if ((new_val & TINT_CSTAT_STATUS(i)) < in exynos4210_pwm_write()
350 s->reg_tint_cstat = new_val; in exynos4210_pwm_write()
/qemu/hw/core/
H A Dregister.c74 uint64_t old_val, new_val, test, no_w_mask; in register_write() local
107 new_val = (val & ~no_w_mask) | (old_val & no_w_mask); in register_write()
108 new_val &= ~(val & ac->w1c); in register_write()
111 new_val = ac->pre_write(reg, new_val); in register_write()
116 new_val); in register_write()
119 register_write_val(reg, new_val); in register_write()
122 ac->post_write(reg, new_val); in register_write()
H A Dqdev-properties-system.c41 const void *old_val, const char *new_val, in check_prop_still_unset() argument
52 prop->driver, prop->property, name, new_val); in check_prop_still_unset()
56 name, new_val); in check_prop_still_unset()
/qemu/rust/hw/timer/hpet/src/
H A Ddevice.rs407 let mut new_val: u64 = old_val.deposit(shift, len, val); in set_tn_cfg_reg() localVariable
408 new_val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); in set_tn_cfg_reg()
411 if deactivating_bit(old_val, new_val, HPET_TN_CFG_INT_TYPE_SHIFT) { in set_tn_cfg_reg()
417 self.config = new_val; in set_tn_cfg_reg()
419 if activating_bit(old_val, new_val, HPET_TN_CFG_INT_ENABLE_SHIFT) && self.is_int_active() { in set_tn_cfg_reg()
629 let mut new_val = old_val.deposit(shift, len, val); in set_cfg_reg() localVariable
631 new_val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); in set_cfg_reg()
632 self.config.set(new_val); in set_cfg_reg()
634 if activating_bit(old_val, new_val, HPET_CFG_ENABLE_SHIFT) { in set_cfg_reg()
647 } else if deactivating_bit(old_val, new_val, HPET_CFG_ENABLE_SHIFT) { in set_cfg_reg()
[all …]
/qemu/hw/remote/
H A Dproxy.c294 uint32_t orig_val, new_val, base_class, val; in probe_pci_info() local
341 new_val = 0xffffffff; in probe_pci_info()
342 config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4, in probe_pci_info()
344 config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4, in probe_pci_info()
346 size = (~(new_val & 0xFFFFFFF0)) + 1; in probe_pci_info()
349 type = (new_val & 0x1) ? in probe_pci_info()
/qemu/rust/hw/char/pl011/src/
H A Ddevice.rs241 let new_val: registers::LineControl = value.into(); in write() localVariable
243 if self.line_control.fifos_enabled() != new_val.fifos_enabled() { in write()
247 let update = (self.line_control.send_break() != new_val.send_break()) && { in write()
248 let break_enable = new_val.send_break(); in write()
252 self.line_control = new_val; in write()
/qemu/hw/display/
H A Djazz_led.c66 uint8_t new_val = val & 0xff; in jazz_led_write() local
68 trace_jazz_led_write(addr, new_val); in jazz_led_write()
70 s->segments = new_val; in jazz_led_write()
/qemu/tests/tcg/multiarch/gdbstub/
H A Dregisters.py187 new_val = frame.read_register(name)
192 if new_val != old_val:
/qemu/hw/net/
H A Dtulip.c712 uint32_t new_val) in tulip_csr9_write() argument
714 if (new_val & CSR9_SR) { in tulip_csr9_write()
716 !!(new_val & CSR9_SR_CS), in tulip_csr9_write()
717 !!(new_val & CSR9_SR_SK), in tulip_csr9_write()
718 !!(new_val & CSR9_SR_DI)); in tulip_csr9_write()
H A Dtrace-events211 e1000e_irq_fix_icr_asserted(uint32_t new_val) "ICR_ASSERTED bit fixed: 0x%x"
212 e1000e_irq_add_msi_other(uint32_t new_val) "ICR_OTHER bit added: 0x%x"
/qemu/target/arm/
H A Dptw.c737 uint64_t new_val, S1Translate *ptw, in arm_casq_ptw() argument
769 address_space_stq_be(as, ptw->out_phys, new_val, attrs, &result); in arm_casq_ptw()
778 cur_val = new_val; in arm_casq_ptw()
791 address_space_stq_le(as, ptw->out_phys, new_val, attrs, &result); in arm_casq_ptw()
800 cur_val = new_val; in arm_casq_ptw()
844 new_val = cpu_to_be64(new_val); in arm_casq_ptw()
845 cur_val = qatomic_cmpxchg__nocheck((uint64_t *)host, old_val, new_val); in arm_casq_ptw()
849 new_val = cpu_to_le64(new_val); in arm_casq_ptw()
850 cur_val = qatomic_cmpxchg__nocheck((uint64_t *)host, old_val, new_val); in arm_casq_ptw()
/qemu/hw/misc/
H A Dxlnx-versal-crl.c77 #define REGFIELD_RESET(type, s, reg, f, new_val, dev) { \ argument
79 bool new_f = FIELD_EX32(new_val, reg, f); \
/qemu/hw/xen/
H A Dxen_pt_config_init.c1971 uint32_t new_val; in xen_pt_config_reg_init() local
1977 new_val = XEN_PT_MERGE_VALUE(val, data, host_mask) & size_mask; in xen_pt_config_reg_init()
1981 new_val |= ((val | data)) & ~size_mask; in xen_pt_config_reg_init()
1983 offset, data, val, new_val); in xen_pt_config_reg_init()
1984 val = new_val; in xen_pt_config_reg_init()
/qemu/target/hexagon/
H A Dgenptr.c59 static inline void gen_masked_reg_write(TCGv new_val, TCGv cur_val, in gen_masked_reg_write() argument
66 tcg_gen_andi_tl(new_val, new_val, ~reg_mask); in gen_masked_reg_write()
68 tcg_gen_or_tl(new_val, new_val, tmp); in gen_masked_reg_write()
/qemu/tcg/
H A Dtcg-op-ldst.c1108 TCGArg idx, MemOp memop, bool new_val, in do_nonatomic_op_i32() argument
1121 tcg_gen_ext_i32(ret, (new_val ? t2 : t1), memop); in do_nonatomic_op_i32()
1149 TCGArg idx, MemOp memop, bool new_val, in do_nonatomic_op_i64() argument
1162 tcg_gen_ext_i64(ret, (new_val ? t2 : t1), memop); in do_nonatomic_op_i64()
/qemu/include/system/
H A Dmemory.h910 int old_val, int new_val);
929 int old_val, int new_val);
/qemu/hw/i386/
H A Dintel_iommu.c173 uint32_t new_val = (ldl_le_p(&s->csr[addr]) & ~clear) | mask; in vtd_set_clear_mask_long() local
174 stl_le_p(&s->csr[addr], new_val); in vtd_set_clear_mask_long()
175 return new_val; in vtd_set_clear_mask_long()
181 uint64_t new_val = (ldq_le_p(&s->csr[addr]) & ~clear) | mask; in vtd_set_clear_mask_quad() local
182 stq_le_p(&s->csr[addr], new_val); in vtd_set_clear_mask_quad()
183 return new_val; in vtd_set_clear_mask_quad()
/qemu/hw/ssi/
H A Dxlnx-versal-ospi.c1248 static bool ind_wr_clearing_op_done(XlnxVersalOspi *s, uint64_t new_val) in ind_wr_clearing_op_done() argument
1252 bool set_in_new_val = FIELD_EX32(new_val, INDIRECT_WRITE_XFER_CTRL_REG, in ind_wr_clearing_op_done()