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Searched refs:ir (Results 1 – 18 of 18) sorted by relevance

/qemu/linux-user/alpha/
H A Dcpu_loop.c75 trapnr = env->ir[IR_V0]; in cpu_loop()
77 env->ir[IR_A0], env->ir[IR_A1], in cpu_loop()
78 env->ir[IR_A2], env->ir[IR_A3], in cpu_loop()
79 env->ir[IR_A4], env->ir[IR_A5], in cpu_loop()
91 trapnr = (env->ir[IR_V0] != 0 && sysret < 0); in cpu_loop()
92 env->ir[IR_V0] = (trapnr ? -sysret : sysret); in cpu_loop()
93 env->ir[IR_A3] = trapnr; in cpu_loop()
113 switch (env->ir[IR_A0]) { in cpu_loop()
181 env->ir[i] = ((abi_ulong *)regs)[i]; in target_cpu_copy_regs()
183 env->ir[IR_SP] = regs->usp; in target_cpu_copy_regs()
H A Dsignal.c80 __put_user(env->ir[i], &sc->sc_regs[i]); in setup_sigcontext()
104 __get_user(env->ir[i], &sc->sc_regs[i]); in restore_sigcontext()
154 env->ir[IR_RA] = r26; in setup_frame()
155 env->ir[IR_PV] = env->pc = ka->_sa_handler; in setup_frame()
156 env->ir[IR_A0] = sig; in setup_frame()
157 env->ir[IR_A1] = 0; in setup_frame()
158 env->ir[IR_A2] = frame_addr + offsetof(struct target_sigframe, sc); in setup_frame()
159 env->ir[IR_SP] = frame_addr; in setup_frame()
201 env->ir[IR_RA] = r26; in setup_rt_frame()
202 env->ir[IR_PV] = env->pc = ka->_sa_handler; in setup_rt_frame()
[all …]
H A Dtarget_cpu.h26 env->ir[IR_SP] = newsp; in cpu_clone_regs_child()
28 env->ir[IR_V0] = 0; in cpu_clone_regs_child()
29 env->ir[IR_A3] = 0; in cpu_clone_regs_child()
30 env->ir[IR_A4] = 1; /* OSF/1 secondary return: child */ in cpu_clone_regs_child()
41 env->ir[IR_A4] = 0; in cpu_clone_regs_parent()
52 return state->ir[IR_SP]; in get_sp_from_cpustate()
/qemu/hw/timer/
H A Dimx_gpt.c59 VMSTATE_UINT32(ir, IMXGPTState),
157 if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) { in imx_gpt_update_int()
214 if (s->ir & GPT_IR_OF1IE) { in imx_gpt_compute_next_timeout()
217 if (s->ir & GPT_IR_OF2IE) { in imx_gpt_compute_next_timeout()
220 if (s->ir & GPT_IR_OF3IE) { in imx_gpt_compute_next_timeout()
227 if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) { in imx_gpt_compute_next_timeout()
230 if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) { in imx_gpt_compute_next_timeout()
233 if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) { in imx_gpt_compute_next_timeout()
236 if ((s->ir & GPT_IR_ROVIE) && (timeout == GPT_TIMER_MAX)) { in imx_gpt_compute_next_timeout()
282 reg_value = s->ir; in imx_gpt_read()
[all …]
/qemu/hw/intc/
H A Drx_icu.c126 icu->ir[n_IRQ] = 0; in rxicu_set_irq()
135 icu->ir[n_IRQ] = 1; in rxicu_set_irq()
153 icu->ir[n_IRQ] = 0; in rxicu_ack_irq()
159 if (icu->ir[i]) { in rxicu_ack_irq()
186 return icu->ir[reg] & R_IR_IR_MASK; in icu_read()
235 icu->ir[reg] = 0; in icu_write()
349 VMSTATE_UINT8_ARRAY(ir, RXICUState, NR_IRQS),
H A Dppc-uic.c54 uint32_t ir, cr; in ppcuic_trigger_irq() local
58 ir = uic->uicsr & uic->uicer & (~uic->uiccr); in ppcuic_trigger_irq()
64 uic->uicsr & uic->uicer, ir, cr); in ppcuic_trigger_irq()
65 if (ir != 0x0000000) { in ppcuic_trigger_irq()
/qemu/target/alpha/
H A Dtranslate.c70 TCGv *ir; member
138 offsetof(CPUAlphaState, ir[i]), in alpha_translate_init()
192 return ctx->ir[reg]; in load_gpr()
204 return ctx->ir[reg]; in load_gpr_lit()
213 return ctx->ir[reg]; in dest_gpr()
346 dest = ctx->ir[ra]; in gen_load_int()
427 tcg_gen_setcond_i64(TCG_COND_EQ, ctx->ir[ra], val, cpu_lock_value); in gen_store_conditional()
433 tcg_gen_movi_i64(ctx->ir[ra], 0); in gen_store_conditional()
462 gen_pc_disp(ctx, ctx->ir[ra], 0); in gen_bdirect()
1034 ld_flag_byte(ctx->ir[ra], ENV_FLAG_RX_SHIFT); in gen_rx()
[all …]
H A Dmachine.c28 VMSTATE_UINTTL_ARRAY(ir, CPUAlphaState, 31),
H A Dhelper.c112 return &env->ir[reg]; in cpu_alpha_addr_gr()
374 env->pc, env->ir[IR_SP]); in alpha_cpu_do_interrupt()
H A Dcpu.h201 uint64_t ir[31]; member
/qemu/include/hw/intc/
H A Drx_icu.h57 uint8_t ir[NR_IRQS]; member
/qemu/include/hw/timer/
H A Dimx_gpt.h103 uint32_t ir; member
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c990 RISCVCPUImpliedExtsRule *ir; in cpu_enable_implied_rule() local
1013 ir = g_hash_table_lookup(misa_ext_implied_rules, in cpu_enable_implied_rule()
1016 if (ir) { in cpu_enable_implied_rule()
1017 cpu_enable_implied_rule(cpu, ir); in cpu_enable_implied_rule()
1028 ir = g_hash_table_lookup(multi_ext_implied_rules, in cpu_enable_implied_rule()
1032 if (ir) { in cpu_enable_implied_rule()
1033 cpu_enable_implied_rule(cpu, ir); in cpu_enable_implied_rule()
/qemu/hw/ppc/
H A Dtrace-events126 ppc4xx_fit(uint32_t ir, uint64_t tcr, uint64_t tsr) "ir %d TCR 0x%" PRIx64 " TSR 0x%" PRIx64
129 ppc4xx_pit(uint32_t ar, uint32_t ir, uint64_t tcr, uint64_t tsr, uint64_t reload) "ar %d ir %d TCR …
/qemu/hw/isa/
H A Dlpc_ich9.c66 static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) in ich9_cc_update_ir() argument
70 irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; in ich9_cc_update_ir()
/qemu/target/microblaze/
H A Dtranslate.c1647 uint32_t ir; in mb_tr_translate_insn() local
1657 ir = translator_ldl_swap(cpu_env(cs), &dc->base, dc->base.pc_next, in mb_tr_translate_insn()
1659 if (!decode(dc, ir)) { in mb_tr_translate_insn()
/qemu/target/rx/
H A Dtranslate.c1450 static inline void rx_rot(int ir, int dir, int rd, int src) in rx_rot() argument
1454 if (ir == ROT_IMM) { in rx_rot()
1462 if (ir == ROT_IMM) { in rx_rot()
/qemu/linux-user/
H A Dsyscall.c1634 cpu_env->ir[IR_A4] = host_pipe[1]; in do_pipe()
9545 cpu_env->ir[IR_A4] = getppid(); in _syscall2()
10131 cpu_env->ir[IR_V0] = 0; /* force no error */ in _syscall2()
10727 cpu_env->ir[IR_V0] = 0; in _syscall2()
12124 cpu_env->ir[IR_A4]=euid; in _syscall2()
12134 cpu_env->ir[IR_A4]=egid; in _syscall2()