70     TCGv *ir;  member
138                                                offsetof(CPUAlphaState, ir[i]),  in alpha_translate_init()
192         return ctx->ir[reg];  in load_gpr()
204         return ctx->ir[reg];  in load_gpr_lit()
213         return ctx->ir[reg];  in dest_gpr()
346     dest = ctx->ir[ra];  in gen_load_int()
427         tcg_gen_setcond_i64(TCG_COND_EQ, ctx->ir[ra], val, cpu_lock_value);  in gen_store_conditional()
433         tcg_gen_movi_i64(ctx->ir[ra], 0);  in gen_store_conditional()
462         gen_pc_disp(ctx, ctx->ir[ra], 0);  in gen_bdirect()
1034         ld_flag_byte(ctx->ir[ra], ENV_FLAG_RX_SHIFT);  in gen_rx()
1054             tcg_gen_ld_i64(ctx->ir[IR_V0], tcg_env,  in gen_call_pal()
1059             tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env,  in gen_call_pal()
1083             tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env,  in gen_call_pal()
1088             tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env,  in gen_call_pal()
1093             tcg_gen_ld_i64(ctx->ir[IR_V0], tcg_env,  in gen_call_pal()
1101             ld_flag_byte(ctx->ir[IR_V0], ENV_FLAG_PS_SHIFT);  in gen_call_pal()
1106                 tcg_gen_andi_i64(tmp, ctx->ir[IR_A0], PS_INT_MASK);  in gen_call_pal()
1116             ld_flag_byte(ctx->ir[IR_V0], ENV_FLAG_PS_SHIFT);  in gen_call_pal()
1121             tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env,  in gen_call_pal()
1126             tcg_gen_ld_i64(ctx->ir[IR_V0], tcg_env,  in gen_call_pal()
1131             tcg_gen_ld32s_i64(ctx->ir[IR_V0], tcg_env,  in gen_call_pal()
1140             tcg_gen_movi_i64(ctx->ir[IR_V0], 0);  in gen_call_pal()
2365             gen_pc_disp(ctx, ctx->ir[ra], 0);  in translate_one()
2874     ctx->ir = cpu_std_ir;  in alpha_tr_init_disas_context()
2878     ctx->ir = (ctx->tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_ir);  in alpha_tr_init_disas_context()