| /qemu/hw/net/ |
| H A D | lan9118_phy.c | 34 qemu_set_irq(s->irq, !!(s->ints & s->int_mask)); in lan9118_phy_update_irq()
71 val = s->int_mask; in lan9118_phy_read()
118 s->int_mask = val & 0xff; in lan9118_phy_write()
169 s->int_mask = 0; in lan9118_phy_reset()
197 VMSTATE_UINT16(int_mask, Lan9118PhyState),
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| H A D | smc91c111.c | 64 uint8_t int_mask; member
93 VMSTATE_UINT8(int_mask, smc91c111_state),
151 level = (s->int_level & s->int_mask) != 0; in smc91c111_update()
376 s->int_mask = 0; in smc91c111_reset()
583 s->int_mask = value; in smc91c111_writeb()
728 return s->int_mask; in smc91c111_readb()
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| /qemu/hw/usb/ |
| H A D | hcd-uhci.c | 641 int status, uint32_t *int_mask) in uhci_handle_td_error() argument
677 *int_mask |= 0x01; in uhci_handle_td_error()
684 uint32_t *int_mask) in uhci_complete_td() argument
698 async->packet.status, int_mask); in uhci_complete_td()
711 *int_mask |= 0x01; in uhci_complete_td()
717 *int_mask |= 0x02; in uhci_complete_td()
732 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask) in uhci_handle_td() argument
774 *int_mask |= 0x01; in uhci_handle_td()
830 int_mask); in uhci_handle_td()
875 ret = uhci_complete_td(s, td, async, int_mask); in uhci_handle_td()
[all …]
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| /qemu/hw/intc/ |
| H A D | loongarch_pch_pic.c | 23 val = mask & s->intirr & ~s->int_mask; in pch_pic_update_irq()
88 val = s->int_mask; in pch_pic_read()
101 val = s->intisr & (~s->int_mask); in pch_pic_read()
134 old = s->int_mask; in pch_pic_write()
135 s->int_mask = (old & ~mask) | data; in pch_pic_write()
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| H A D | loongarch_pic_common.c | 65 s->int_mask = UINT64_MAX; in loongarch_pic_common_reset_hold()
92 VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
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| /qemu/hw/display/ |
| H A D | pl110.c | 70 uint32_t int_mask; member
96 VMSTATE_UINT32(int_mask, PL110State),
371 if (s->int_status & s->int_mask) { in pl110_update()
418 return s->int_mask; in pl110_read()
421 return s->int_mask; in pl110_read()
427 return s->int_status & s->int_mask; in pl110_read()
484 s->int_mask = val; in pl110_write()
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| H A D | qxl.c | 417 d->ram->int_mask = cpu_to_le32(0); in init_qxl_ram()
1078 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 || in interface_client_monitors_config()
1079 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) { in interface_client_monitors_config()
1081 qxl->ram->int_mask, in interface_client_monitors_config()
1198 uint32_t mask = le32_to_cpu(d->ram->int_mask); in qxl_update_irq()
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| H A D | trace-events | 115 qxl_client_monitors_config_unsupported_by_guest(int qid, uint32_t int_mask, void *client_monitors_c…
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| /qemu/hw/net/can/ |
| H A D | ctucan_core.c | 165 int_rq.u32 &= ~s->int_mask.u32; in ctucan_update_irq()
225 s->int_mask.u32 = 0; in ctucan_hardware_reset()
281 s->int_stat.u32 |= int_stat.u32 & ~s->int_mask.u32; in ctucan_send_ready_buffers()
351 s->int_mask.u32 |= (uint32_t)val; in ctucan_mem_write()
354 s->int_mask.u32 &= ~(uint32_t)val; in ctucan_mem_write()
441 val = s->int_mask.u32; in ctucan_mem_read()
553 s->int_stat.u32 |= int_stat.u32 & ~s->int_mask.u32; in ctucan_receive()
564 s->int_stat.u32 |= int_stat.u32 & ~s->int_mask.u32; in ctucan_receive()
643 VMSTATE_UINT32(int_mask.u32, CtuCanCoreState),
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| H A D | ctucan_core.h | 65 union ctu_can_fd_int_mask_set int_mask; member
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| /qemu/include/hw/net/ |
| H A D | lan9118_phy.h | 27 uint16_t int_mask; member
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| /qemu/hw/m68k/ |
| H A D | next-cube.c | 100 uint32_t int_mask; member
216 DPRINTF("MMIO Read INT mask: %x\n", s->int_mask); in next_mmio_read()
217 val = s->int_mask; in next_mmio_read()
252 DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, (unsigned int)val); in next_mmio_write()
253 s->int_mask = val; in next_mmio_write()
520 if (s->int_mask & (1 << shift)) { in next_irq()
1224 VMSTATE_UINT32(int_mask, NeXTPC),
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| /qemu/include/hw/intc/ |
| H A D | loongarch_pic_common.h | 50 uint64_t int_mask; /* 0x020 interrupt mask register */ member
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| /qemu/hw/arm/ |
| H A D | stellaris.c | 102 uint32_t int_mask; member
127 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); in ssys_update()
230 return s->int_mask; in ssys_read()
232 return s->int_status & s->int_mask; in ssys_read()
332 s->int_mask = value & 0x7f; in ssys_write()
452 VMSTATE_UINT32(int_mask, ssys_state),
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