| /qemu/disas/ |
| H A D | nanomips.c | 502 static uint64 extract_code_18_to_0(uint64 instruction) in extract_code_18_to_0() argument
505 value |= extract_bits(instruction, 0, 19); in extract_code_18_to_0()
510 static uint64 extract_shift3_2_1_0(uint64 instruction) in extract_shift3_2_1_0() argument
513 value |= extract_bits(instruction, 0, 3); in extract_shift3_2_1_0()
518 static uint64 extract_u_11_10_9_8_7_6_5_4_3__s3(uint64 instruction) in extract_u_11_10_9_8_7_6_5_4_3__s3() argument
521 value |= extract_bits(instruction, 3, 9) << 3; in extract_u_11_10_9_8_7_6_5_4_3__s3()
526 static uint64 extract_count_3_2_1_0(uint64 instruction) in extract_count_3_2_1_0() argument
529 value |= extract_bits(instruction, 0, 4); in extract_count_3_2_1_0()
534 static uint64 extract_rtz3_9_8_7(uint64 instruction) in extract_rtz3_9_8_7() argument
537 value |= extract_bits(instruction, 7, 3); in extract_rtz3_9_8_7()
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| /qemu/tcg/loongarch64/ |
| H A D | tcg-insn-defs.c.inc | 3 * LoongArch instruction formats, opcodes, and encoders for TCG use.
1318 /* Emits the `movgr2scr td, j` instruction. */
1325 /* Emits the `movscr2gr d, tj` instruction. */
1332 /* Emits the `clz.w d, j` instruction. */
1339 /* Emits the `ctz.w d, j` instruction. */
1346 /* Emits the `clz.d d, j` instruction. */
1353 /* Emits the `ctz.d d, j` instruction. */
1360 /* Emits the `revb.2h d, j` instruction. */
1367 /* Emits the `revb.2w d, j` instruction. */
1374 /* Emits the `revb.d d, j` instruction. */
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| /qemu/target/hexagon/ |
| H A D | attribs_def.h.inc | 22 DEF_ATTRIB(EXTENSION, "Extension instruction", "", "")
36 DEF_ATTRIB(SUBINSN, "sub-instruction", "", "")
53 DEF_ATTRIB(MEMLIKE, "Memory-like instruction", "", "")
65 DEF_ATTRIB(CVI_NEW, "New value memory instruction executes on HVX", "", "")
66 DEF_ATTRIB(CVI_VM, "Memory instruction executes on HVX", "", "")
67 DEF_ATTRIB(CVI_VP, "Permute instruction executes on HVX", "", "")
69 DEF_ATTRIB(CVI_VX, "Multiply instruction executes on HVX", "", "")
71 DEF_ATTRIB(CVI_VS, "Shift instruction executes on HVX", "", "")
74 DEF_ATTRIB(CVI_VA, "ALU instruction executes on HVX", "", "")
75 DEF_ATTRIB(CVI_VA_DV, "Double vector alu instruction executes on HVX", "", "")
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| H A D | README | 1 Hexagon is Qualcomm's very long instruction word (VLIW) digital signal
22 This has all the instruction and packet semantics
26 macros.def Mapping of macros to instruction attributes
27 encode*.def Encoding patterns for each instruction
29 legal VLIW slots for each instruction
31 Parser that, given the high-level definitions of an instruction,
60 Here's an example of the A2_add instruction.
117 The instruction semantics C code relies heavily on macros. In cases where the
159 the instruction. This makes it easy to override the instruction semantics with
160 functions from tcg-op-gvec.h. Here's the override for this instruction.
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| /qemu/qapi/ |
| H A D | replay.json | 50 # instruction count which may be used for @replay-break and
68 # Set replay breakpoint at instruction count @icount. Execution stops
69 # when the specified instruction is reached. There can be at most one
72 # i.e. at instruction counts greater than the current one. The
73 # current instruction count can be observed with @query-replay.
75 # @icount: instruction count to stop at
104 # Automatically proceed to the instruction count @icount, when
106 # snapshot and replays the execution to find the desired instruction.
111 # @icount: target instruction count
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| H A D | machine-s390x.json | 65 # The guest can tell the host (via the PTF instruction) whether the
74 # provisioning the next time it uses the STSI(15) instruction.
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| /qemu/docs/devel/ |
| H A D | tcg-icount.rst | 11 instruction counting during execution. This should not be confused
13 long an instruction would take on real hardware. That is a job for
32 fixed number of ns per instruction or adjusted as execution continues
46 would cause the instruction budget to go negative we exit the main
54 While we can adjust the instruction budget for known events like timer
62 - re-compile a single [1]_ instruction block for the current PC
76 When the translator is handling an instruction of this kind:
88 * it must end the TB immediately after this instruction
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| H A D | decodetree.rst | 7 A *decodetree* is built from instruction *patterns*. A pattern may
8 represent a single architectural instruction or a group of same, depending
37 A *named_field* refers to some other field in the instruction pattern
46 defined in the instruction pattern(s) that use the format.
47 Conversely, an instruction pattern can include fields that refer to
132 across many instruction patterns.
225 instruction::
235 When the *cf* field is zero, the instruction has no side effects,
237 is discarded and so the instruction has no effect. When the *rt2*
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| H A D | s390-dasd-ipl.rst | 24 equivalent of a branch/jump/goto instruction for channel programs.
29 The TIC ccw instruction at the end of the IPL1 channel program will begin
41 as long as the data placed in location ``0x0`` contains a psw whose instruction
50 psw's instruction address will point to the location in memory where we want
52 instruction) causing control to be passed to the operating system code.
116 4. Grab the target address of the TIC instruction from the IPL1 channel program.
127 subchannel to execute the remaining TIC instruction. This causes the entire
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| H A D | tcg-plugins.rst | 44 translation, instruction or operation. The handles themselves are only
102 important to track individual instruction execution you need to
109 Instruction instrumentation runs before the instruction executes. You
110 can be can be sure the instruction will be dispatched, but you can't
112 synchronous exception (e.g. SIGILL) triggered by the instruction
114 instrument the next instruction as well. See the ``execlog.c`` plugin
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| H A D | tcg.rst | 8 it converts it to the host instruction set. Usually dynamic translators
88 instruction that later on gets translated to a jump to an address
109 is still in memory) and will jump directly to the first instruction of
131 instruction cache invalidation is signaled by the application when code
167 Arm, and so on. This state is stored for each target instruction, and
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| H A D | tcg-ops.rst | 38 any branch instruction.
50 are strongly typed. Each instruction has a fixed number of output
53 the vector. The notable exception is the call instruction which has
58 included in the instruction name. Constants are prefixed with a '$'.
211 only the last instruction is kept.
683 - | Generate a target memory barrier instruction to ensure memory ordering
684 as being enforced by a corresponding guest memory barrier instruction.
689 instruction. The backend should take care to emit the target barrier
690 instruction only when necessary i.e., for SMP guests and when MTTCG is
971 instruction. Memory constraints are not supported in this
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| /qemu/target/mips/tcg/ |
| H A D | tx79.decode | 1 # Toshiba C790's instruction set
12 # instruction patterns.
19 # Named instruction formats. These are generally used to
20 # reduce the amount of duplication between instruction patterns.
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| H A D | nanomips_translate.c.inc | 70 /* POOL32A instruction pool */
80 /* P.GP.W instruction pool */
87 /* P48I instruction pool */
97 /* P.U12 instruction pool */
113 /* POOL32F instruction pool */
120 /* POOL32S instruction pool */
126 /* P.LUI instruction pool */
132 /* P.GP.BH instruction pool */
143 /* P.LS.U12 instruction pool */
161 /* P.LS.S9 instruction pool */
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| H A D | vr54xx.decode | 1 # MIPS VR5432 instruction set extensions
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| /qemu/target/hexagon/idef-parser/ |
| H A D | README.rst | 1 Hexagon ISA instruction definitions to tinycode generator compiler
11 example. Let's start by one of the simplest Hexagon instruction: the ``add``.
13 The ISA description language represents the ``add`` instruction as
45 Let's begin by describing the input code. The ``add`` instruction is associated
47 variants of the same instruction, and expresses the class to which the
48 instruction belongs, in this case ``A2`` corresponds to the Hexagon
49 ``ALU32/ALU`` instruction subclass.
51 After the instruction identifier, we have a series of parameters that represents
62 Let's now observe the actual instruction description code, in this case:
109 instruction semantics in ``semantics_generated.pyinc`` that we need to consider.
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| /qemu/docs/system/riscv/ |
| H A D | microblaze-v-generic.rst | 5 64-bit) RISC-V instruction set architecture (ISA) and contains interfaces
24 - RV32I base integer instruction set
26 - "Zifencei" instruction-fetch
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| /qemu/docs/system/openrisc/ |
| H A D | emulation.rst | 7 The or1200 cpu also has support for the following instruction subsets:
12 In addition to the instruction subsets the QEMU TCG emulation also has support
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| /qemu/target/s390x/ |
| H A D | cpu_features_def.h.inc | 22 /* Features exposed via the STFL(E) instruction. */
64 DEF_FEAT(PFPO, "pfpo", STFL, 44, "PFPO instruction")
75 DEF_FEAT(MISC_INSTRUCTION_EXT2, "minste2", STFL, 58, "Miscellaneous-instruction-extensions facility…
94 DEF_FEAT(SIF, "sif", STFL, 85, "Sequential-instruction-fetching facility")
152 * Features exposed via no feature bit (but e.g., instruction sensing)
159 /* Features exposed via the PLO instruction. */
223 /* Features exposed via the PTFF instruction. */
237 /* Features exposed via the KMAC instruction. */
260 /* Features exposed via the KMC instruction. */
275 /* Features exposed via the KM instruction. */
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| /qemu/hw/acpi/ |
| H A D | erst.c | 190 uint8_t instruction; member
209 build_append_int_noprefix(e->table_data, e->instruction, 1); in build_serialization_instruction()
246 .instruction = INST_READ_REGISTER_VALUE, in build_erst()
252 .instruction = INST_READ_REGISTER, in build_erst()
258 .instruction = INST_READ_REGISTER, in build_erst()
264 .instruction = INST_WRITE_REGISTER_VALUE, in build_erst()
270 .instruction = INST_WRITE_REGISTER, in build_erst()
276 .instruction = INST_WRITE_REGISTER, in build_erst()
282 .instruction = INST_WRITE_REGISTER_VALUE, in build_erst()
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| /qemu/target/ppc/translate/ |
| H A D | misc-impl.c.inc | 87 * BookE uses the mbar instruction instead of eieio, which is basically
126 * POWER9 has a eieio instruction variant using bit 6 as a hint to
133 * as this is not an instruction software should be using,
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| /qemu/hw/dma/ |
| H A D | trace-events | 38 pl330_chan_exec_undef(void) "undefined instruction"
43 pl330_debug_exec_stall(void) "stall of debug instruction not implemented"
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| /qemu/target/arm/tcg/ |
| H A D | vfp-uncond.decode | 1 # AArch32 VFP instruction descriptions (unconditional insns)
33 # Each individual instruction function must do the checks for
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| /qemu/docs/system/arm/ |
| H A D | emulation.rst | 42 - FEAT_DPB (DC CVAP instruction)
43 - FEAT_DPB2 (DC CVADP instruction)
107 - FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN)
132 - FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode)
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| /qemu/target/loongarch/ |
| H A D | insns.decode | 3 # LoongArch instruction decode definitions.
106 # Fixed point arithmetic operation instruction
156 # Fixed point shift operation instruction
176 # Fixed point bit operation instruction
208 # Fixed point load/store instruction
258 # Fixed point atomic instruction
302 # Fixed point extra instruction
322 # Floating point arithmetic operation instruction
368 # Floating point compare instruction
374 # Floating point conversion instruction
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