1*b14df228SStafford HorneOpenRISC 1000 CPU architecture support 2*b14df228SStafford Horne====================================== 3*b14df228SStafford Horne 4*b14df228SStafford HorneQEMU's TCG emulation includes support for the OpenRISC or1200 implementation of 5*b14df228SStafford Hornethe OpenRISC 1000 cpu architecture. 6*b14df228SStafford Horne 7*b14df228SStafford HorneThe or1200 cpu also has support for the following instruction subsets: 8*b14df228SStafford Horne 9*b14df228SStafford Horne- ORBIS32 (OpenRISC Basic Instruction Set) 10*b14df228SStafford Horne- ORFPX32 (OpenRISC Floating-Point eXtension) 11*b14df228SStafford Horne 12*b14df228SStafford HorneIn addition to the instruction subsets the QEMU TCG emulation also has support 13*b14df228SStafford Hornefor most Class II (optional) instructions. 14*b14df228SStafford Horne 15*b14df228SStafford HorneFor information on all OpenRISC instructions please refer to the latest 16*b14df228SStafford Hornearchitecture manual available on the OpenRISC website in the 17*b14df228SStafford Horne`OpenRISC Architecture <https://openrisc.io/architecture>`_ section. 18