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Searched refs:ics (Results 1 – 15 of 15) sorted by relevance

/qemu/hw/intc/
H A Dxics.c70 void ics_pic_print_info(ICSState *ics, GString *buf) in ics_pic_print_info() argument
75 ics->offset, ics->offset + ics->nr_irqs - 1, ics); in ics_pic_print_info()
77 if (!ics->irqs) { in ics_pic_print_info()
82 ics_synchronize_state(ics); in ics_pic_print_info()
85 for (i = 0; i < ics->nr_irqs; i++) { in ics_pic_print_info()
86 ICSIRQState *irq = ics->irqs + i; in ics_pic_print_info()
92 ics->offset + i, in ics_pic_print_info()
109 static void ics_reject(ICSState *ics, uint32_t nr);
110 static void ics_eoi(ICSState *ics, uint32_t nr);
202 ICSState *ics; in icp_eoi() local
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H A Dxics_spapr.c156 ICSState *ics = spapr->ics; in rtas_set_xive() local
165 if (!ics) { in rtas_set_xive()
174 if (!ics_valid_irq(ics, nr) || !xics_icp_get(XICS_FABRIC(spapr), server) in rtas_set_xive()
180 srcno = nr - ics->offset; in rtas_set_xive()
181 ics_write_xive(ics, srcno, server, priority, priority); in rtas_set_xive()
191 ICSState *ics = spapr->ics; in rtas_get_xive() local
200 if (!ics) { in rtas_get_xive()
207 if (!ics_valid_irq(ics, nr)) { in rtas_get_xive()
213 srcno = nr - ics->offset; in rtas_get_xive()
214 rtas_st(rets, 1, ics->irqs[srcno].server); in rtas_get_xive()
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H A Dxics_kvm.c185 void ics_get_kvm_state(ICSState *ics) in ics_get_kvm_state() argument
195 for (i = 0; i < ics->nr_irqs; i++) { in ics_get_kvm_state()
196 ICSIRQState *irq = &ics->irqs[i]; in ics_get_kvm_state()
198 if (ics_irq_free(ics, i)) { in ics_get_kvm_state()
203 i + ics->offset, &state, false, &error_fatal); in ics_get_kvm_state()
247 void ics_synchronize_state(ICSState *ics) in ics_synchronize_state() argument
249 ics_get_kvm_state(ics); in ics_synchronize_state()
252 int ics_set_kvm_state_one(ICSState *ics, int srcno, Error **errp) in ics_set_kvm_state_one() argument
255 ICSIRQState *irq = &ics->irqs[srcno]; in ics_set_kvm_state_one()
292 srcno + ics->offset, &state, true, errp); in ics_set_kvm_state_one()
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/qemu/hw/pci-host/
H A Dpnv_phb3_msi.c101 ICSState *ics = ICS(msi); in phb3_msi_try_send() local
132 icp_irq(ics, server, srcno + ics->offset, prio); in phb3_msi_try_send()
160 ICSState *ics = ICS(msi); in pnv_phb3_msi_send() local
165 if (src >= ics->nr_irqs) { in pnv_phb3_msi_send()
193 static void phb3_msi_reject(ICSState *ics, uint32_t nr) in phb3_msi_reject() argument
195 Phb3MsiState *msi = PHB3_MSI(ics); in phb3_msi_reject()
196 unsigned int srcno = nr - ics->offset; in phb3_msi_reject()
206 static void phb3_msi_resend(ICSState *ics) in phb3_msi_resend() argument
208 Phb3MsiState *msi = PHB3_MSI(ics); in phb3_msi_resend()
246 ICSState *ics = ICS(msi); in pnv_phb3_msi_update_config() local
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H A Dpnv_phb3.c352 ICSState *ics = &phb->lsis; in pnv_phb3_remap_irqs() local
364 ics->offset = 0; in pnv_phb3_remap_irqs()
379 ics->offset = 0; in pnv_phb3_remap_irqs()
407 ics->offset = comp + global; in pnv_phb3_remap_irqs()
/qemu/include/hw/ppc/
H A Dxics.h116 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr) in ics_valid_irq() argument
118 return (nr >= ics->offset) && (nr < (ics->offset + ics->nr_irqs)); in ics_valid_irq()
161 void icp_irq(ICSState *ics, int server, int nr, uint8_t priority);
164 void ics_write_xive(ICSState *ics, int nr, int server,
168 static inline bool ics_irq_free(ICSState *ics, uint32_t srcno) in ics_irq_free() argument
170 return !(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK); in ics_irq_free()
173 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
175 void ics_pic_print_info(ICSState *ics, GString *buf);
177 void ics_resend(ICSState *ics);
190 void ics_get_kvm_state(ICSState *ics);
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H A Dpnv_psi.h59 ICSState ics; member
H A Dspapr.h272 ICSState *ics; member
/qemu/hw/ppc/
H A Dspapr_irq.c208 { SPAPR_INTC((spapr_)->ics), SPAPR_INTC((spapr_)->xive), }
325 spapr->ics = ICS_SPAPR(obj); in spapr_irq_init()
432 if (spapr->ics) { in spapr_qirq()
433 assert(ics_valid_irq(spapr->ics, irq)); in spapr_qirq()
518 if (!spapr->ics) { in spapr_irq_update_active_intc()
530 new_intc = SPAPR_INTC(spapr->ics); in spapr_irq_update_active_intc()
540 static int ics_find_free_block(ICSState *ics, int num, int alignnum) in ics_find_free_block() argument
544 for (first = 0; first < ics->nr_irqs; first += alignnum) { in ics_find_free_block()
545 if (num > (ics->nr_irqs - first)) { in ics_find_free_block()
549 if (!ics_irq_free(ics, i)) { in ics_find_free_block()
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H A Dpnv_psi.c168 ICSState *ics = &PNV8_PSI(psi)->ics; in pnv_psi_set_irsn() local
185 ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH; in pnv_psi_set_irsn()
269 ICSState *ics = &PNV8_PSI(psi)->ics; in pnv_psi_set_xivr() local
305 ics_write_xive(ics, src, server, prio, prio); in pnv_psi_set_xivr()
477 object_initialize_child(obj, "ics-psi", &psi8->ics, TYPE_ICS); in pnv_psi_power8_instance_init()
478 object_property_add_alias(obj, ICS_PROP_XICS, OBJECT(&psi8->ics), in pnv_psi_power8_instance_init()
494 ICSState *ics = &PNV8_PSI(psi)->ics; in pnv_psi_power8_realize() local
498 if (!object_property_set_int(OBJECT(ics), "nr-irqs", PSI_NUM_INTERRUPTS, in pnv_psi_power8_realize()
502 if (!qdev_realize(DEVICE(ics), NULL, errp)) { in pnv_psi_power8_realize()
506 for (i = 0; i < ics->nr_irqs; i++) { in pnv_psi_power8_realize()
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H A Dpnv.c835 ics_pic_print_info(&chip8->psi.ics, buf); in pnv_chip_power8_pic_print_info()
2529 if (ics_valid_irq(&chip8->psi.ics, irq)) { in pnv_ics_get()
2530 return &chip8->psi.ics; in pnv_ics_get()
2570 ics_resend(&chip8->psi.ics); in pnv_ics_resend()
H A Dspapr.c4442 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; in spapr_ics_get()
4449 ics_resend(spapr->ics); in spapr_ics_resend()
/qemu/hw/audio/
H A Dintel-hda.c177 uint32_t ics; member
311 if (d->ics & ICH6_IRS_BUSY) { in intel_hda_corb_run()
350 if (d->ics & ICH6_IRS_BUSY) { in intel_hda_response()
354 d->ics &= ~(ICH6_IRS_BUSY | 0xf0); in intel_hda_response()
355 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4)); in intel_hda_response()
571 if (d->ics & ICH6_IRS_BUSY) { in intel_hda_set_ics()
802 .offset = offsetof(IntelHDAState, ics),
1204 VMSTATE_UINT32(ics, IntelHDAState),
/qemu/include/hw/pci-host/
H A Dpnv_phb3.h30 ICSState ics; member
/qemu/hw/net/
H A Dtrace-events216 e1000e_irq_read_ics(uint32_t ics) "Current ICS: 0x%x"