168     ICSState *ics = &PNV8_PSI(psi)->ics;  in pnv_psi_set_irsn()  local
185     ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH;  in pnv_psi_set_irsn()
269     ICSState *ics = &PNV8_PSI(psi)->ics;  in pnv_psi_set_xivr()  local
305     ics_write_xive(ics, src, server, prio, prio);  in pnv_psi_set_xivr()
477     object_initialize_child(obj, "ics-psi", &psi8->ics, TYPE_ICS);  in pnv_psi_power8_instance_init()
478     object_property_add_alias(obj, ICS_PROP_XICS, OBJECT(&psi8->ics),  in pnv_psi_power8_instance_init()
494     ICSState *ics = &PNV8_PSI(psi)->ics;  in pnv_psi_power8_realize()  local
498     if (!object_property_set_int(OBJECT(ics), "nr-irqs", PSI_NUM_INTERRUPTS,  in pnv_psi_power8_realize()
502     if (!qdev_realize(DEVICE(ics), NULL, errp)) {  in pnv_psi_power8_realize()
506     for (i = 0; i < ics->nr_irqs; i++) {  in pnv_psi_power8_realize()
507         ics_set_irq_type(ics, i, true);  in pnv_psi_power8_realize()
510     qdev_init_gpio_in(dev, pnv_psi_power8_set_irq, ics->nr_irqs);  in pnv_psi_power8_realize()
512     psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);  in pnv_psi_power8_realize()