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Searched refs:halt (Results 1 – 12 of 12) sorted by relevance

/qemu/docs/specs/
H A Dvirt-ctlr.rst22 are reset (1), halt (2) and panic (3).
/qemu/hw/ide/
H A Dahci.c651 ncq_tfs->halt = false; in ahci_reset_port()
1025 ncq_tfs->halt = true; in ncq_cb()
1035 if (!ncq_tfs->halt) { in ncq_cb()
1062 ncq_tfs->halt = false; in execute_ncq_command()
1457 if (ncq_tfs->halt) { in ahci_restart()
1664 VMSTATE_BOOL(halt, NCQTransferState),
1734 if (ncq_tfs->used != ncq_tfs->halt) { in ahci_state_post_load()
1737 if (!ncq_tfs->halt) { in ahci_state_post_load()
H A Dahci-internal.h304 bool halt; member
/qemu/docs/system/arm/
H A Dmps2.rst55 - AN536 does not support runtime control of CPU reset and halt via
66 held in halt via the initial SCC CFG_REG0 register setting. You can
/qemu/target/hppa/
H A Dsys_helper.c51 void HELPER(halt)(CPUHPPAState *env) in HELPER() argument
H A Dhelper.h85 DEF_HELPER_1(halt, noreturn, env)
H A Dinsns.decode139 halt 1111 1111 1111 1101 1110 1010 1101 0000
/qemu/target/ppc/
H A Dtrace-events25 kvm_handle_halt(void) "handle halt"
/qemu/target/alpha/
H A Dhelper.h95 DEF_HELPER_1(halt, void, i64)
/qemu/hw/usb/
H A Dtrace-events94 …(uint32_t addr, int ioc, int active, int halt, int babble, int xacterr) "QTD @ 0x%08x - ioc %d, ac…
/qemu/docs/devel/
H A Dmulti-thread-tcg.rst198 - cross vCPU TLB flush may need other vCPU brought to halt
/qemu/target/m68k/
H A Dtranslate.c4505 DISAS_INSN(halt) in DISAS_INSN() argument
5855 INSN(halt, 4ac8, ffff, CF_ISA_A); in register_m68k_insns()
5856 INSN(halt, 4ac8, ffff, M68K); in register_m68k_insns()