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Searched refs:gic (Results 1 – 25 of 57) sorted by relevance

123

/qemu/hw/intc/
H A Dmips_gic.c25 static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp, int pin) in mips_gic_set_vp_irq() argument
31 for (i = 0; i < gic->num_irq; i++) { in mips_gic_set_vp_irq()
32 if ((gic->irq_state[i].map_pin & GIC_MAP_MSK) == pin && in mips_gic_set_vp_irq()
33 gic->irq_state[i].map_vp == vp && in mips_gic_set_vp_irq()
34 gic->irq_state[i].enabled) { in mips_gic_set_vp_irq()
35 ored_level |= gic->irq_state[i].pending; in mips_gic_set_vp_irq()
42 if (((gic->vps[vp].compare_map & GIC_MAP_MSK) == pin) && in mips_gic_set_vp_irq()
43 (gic->vps[vp].mask & GIC_VP_MASK_CMP_MSK)) { in mips_gic_set_vp_irq()
45 ored_level |= (gic->vps[vp].pend & GIC_VP_MASK_CMP_MSK) >> in mips_gic_set_vp_irq()
49 kvm_mips_set_ipi_interrupt(env_archcpu(gic->vps[vp].env), in mips_gic_set_vp_irq()
[all …]
H A Drealview_gic.c21 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in realview_gic_set_irq()
35 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", numirq); in realview_gic_realize()
36 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { in realview_gic_realize()
39 busdev = SYS_BUS_DEVICE(&s->gic); in realview_gic_realize()
62 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); in realview_gic_init()
63 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", 1); in realview_gic_init()
H A Darm_gicv3.c120 if (cs->gic->gicd_ctlr & GICD_CTLR_DS) { in gicr_int_pending()
127 if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1NS) { in gicr_int_pending()
130 if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1S) { in gicr_int_pending()
133 if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP0) { in gicr_int_pending()
149 nmi = *gic_bmp_ptr32(cs->gic->nmi, irq); in gicv3_get_priority()
155 if (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) && in gicv3_get_priority()
157 (!is_redist && gicv3_gicd_group_test(cs->gic, irq)))) { in gicv3_get_priority()
169 *prio = cs->gic->gicd_ipriority[irq]; in gicv3_get_priority()
210 cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq); in gicv3_redist_update_noirqset()
213 if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable && in gicv3_redist_update_noirqset()
[all …]
H A Darm_gicv3_redist.c24 if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) { in mask_group()
105 address_space_read(&cs->gic->dma_as, in update_for_one_lpi()
154 AddressSpace *as = &cs->gic->dma_as; in update_for_all_lpis()
186 AddressSpace *as = &cs->gic->dma_as; in set_pending_table_bit()
211 if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) { in gicr_read_ipriorityr()
229 if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) { in gicr_write_ipriorityr()
385 if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) { in gicr_readl()
422 *data = cs->gic->nmi_support ? in gicr_readl()
440 if ((cs->gic->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { in gicr_readl()
450 if ((cs->gic->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) { in gicr_readl()
[all …]
H A Dexynos4210_gic.c51 qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); in exynos4210_gic_set_irq()
63 s->gic = qdev_new("arm_gic"); in exynos4210_gic_realize()
64 qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); in exynos4210_gic_realize()
65 qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ); in exynos4210_gic_realize()
66 gicbusdev = SYS_BUS_DEVICE(s->gic); in exynos4210_gic_realize()
/qemu/hw/arm/
H A Dallwinner-h3.c205 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); in allwinner_h3_init()
267 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI + in allwinner_h3_realize()
269 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); in allwinner_h3_realize()
270 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS); in allwinner_h3_realize()
271 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false); in allwinner_h3_realize()
272 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true); in allwinner_h3_realize()
273 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal); in allwinner_h3_realize()
275 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_DEV_GIC_DIST]); in allwinner_h3_realize()
276 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_DEV_GIC_CPU]); in allwinner_h3_realize()
277 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_DEV_GIC_HYP]); in allwinner_h3_realize()
[all …]
H A Dbcm2838.c44 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in bcm2838_gic_set_irq()
62 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); in bcm2838_init()
107 if (!object_property_set_uint(OBJECT(&s->gic), "revision", 2, errp)) { in bcm2838_realize()
111 if (!object_property_set_uint(OBJECT(&s->gic), "num-cpu", BCM283X_NCPUS, in bcm2838_realize()
116 if (!object_property_set_uint(OBJECT(&s->gic), "num-irq", in bcm2838_realize()
121 if (!object_property_set_bool(OBJECT(&s->gic), in bcm2838_realize()
127 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { in bcm2838_realize()
131 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, in bcm2838_realize()
133 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, in bcm2838_realize()
135 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, in bcm2838_realize()
[all …]
H A Dallwinner-r40.c276 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); in allwinner_r40_init()
341 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_R40_GIC_NUM_SPI + in allwinner_r40_realize()
343 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); in allwinner_r40_realize()
344 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_R40_NUM_CPUS); in allwinner_r40_realize()
345 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false); in allwinner_r40_realize()
346 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true); in allwinner_r40_realize()
347 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal); in allwinner_r40_realize()
349 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_R40_DEV_GIC_DIST]); in allwinner_r40_realize()
350 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_R40_DEV_GIC_CPU]); in allwinner_r40_realize()
351 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_R40_DEV_GIC_HYP]); in allwinner_r40_realize()
[all …]
H A Dxlnx-zynqmp.c256 static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic) in xlnx_zynqmp_create_bbram() argument
269 sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]); in xlnx_zynqmp_create_bbram()
272 static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic) in xlnx_zynqmp_create_efuse() argument
294 sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]); in xlnx_zynqmp_create_efuse()
297 static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState *s, qemu_irq *gic) in xlnx_zynqmp_create_apu_ctrl() argument
315 sysbus_connect_irq(sbd, 0, gic[APU_IRQ]); in xlnx_zynqmp_create_apu_ctrl()
318 static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic) in xlnx_zynqmp_create_crf() argument
327 sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]); in xlnx_zynqmp_create_crf()
330 static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic) in xlnx_zynqmp_create_ttc() argument
343 sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]); in xlnx_zynqmp_create_ttc()
[all …]
H A Dfsl-imx6.c121 DeviceState *gic; in fsl_imx6_realize() local
158 gic = mpcore; in fsl_imx6_realize()
160 sysbus_connect_irq(SYS_BUS_DEVICE(gic), i, in fsl_imx6_realize()
162 sysbus_connect_irq(SYS_BUS_DEVICE(gic), i + smp_cpus, in fsl_imx6_realize()
200 qdev_get_gpio_in(gic, serial_table[i].irq)); in fsl_imx6_realize()
211 qdev_get_gpio_in(gic, FSL_IMX6_GPT_IRQ)); in fsl_imx6_realize()
231 qdev_get_gpio_in(gic, epit_table[i].irq)); in fsl_imx6_realize()
251 qdev_get_gpio_in(gic, i2c_table[i].irq)); in fsl_imx6_realize()
308 qdev_get_gpio_in(gic, gpio_table[i].irq_low)); in fsl_imx6_realize()
310 qdev_get_gpio_in(gic, gpio_table[i].irq_high)); in fsl_imx6_realize()
[all …]
H A Dsbsa-ref.c106 DeviceState *gic; member
424 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(sms->gic), in create_its()
441 sms->gic = qdev_new(gictype); in create_gic()
442 qdev_prop_set_uint32(sms->gic, "revision", 3); in create_gic()
443 qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus); in create_gic()
448 qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32); in create_gic()
449 qdev_prop_set_bit(sms->gic, "has-security-extensions", true); in create_gic()
457 qdev_prop_set_array(sms->gic, "redist-region-count", redist_region_count); in create_gic()
459 object_property_set_link(OBJECT(sms->gic), "sysmem", in create_gic()
461 qdev_prop_set_bit(sms->gic, "has-lpi", true); in create_gic()
[all …]
H A Dfsl-imx7.c170 DeviceState *gic; in fsl_imx7_realize() local
215 gic = mpcore; in fsl_imx7_realize()
217 SysBusDevice *sbd = SYS_BUS_DEVICE(gic); in fsl_imx7_realize()
258 qdev_get_gpio_in(gic, FSL_IMX7_GPTn_IRQ[i])); in fsl_imx7_realize()
300 qdev_get_gpio_in(gic, FSL_IMX7_GPIOn_LOW_IRQ[i])); in fsl_imx7_realize()
303 qdev_get_gpio_in(gic, FSL_IMX7_GPIOn_HIGH_IRQ[i])); in fsl_imx7_realize()
355 qdev_get_gpio_in(gic, FSL_IMX7_SPIn_IRQ[i])); in fsl_imx7_realize()
380 qdev_get_gpio_in(gic, FSL_IMX7_I2Cn_IRQ[i])); in fsl_imx7_realize()
414 irq = qdev_get_gpio_in(gic, FSL_IMX7_UARTn_IRQ[i]); in fsl_imx7_realize()
452 irq = qdev_get_gpio_in(gic, FSL_IMX7_ENET_IRQ(i, 0)); in fsl_imx7_realize()
[all …]
H A Dfsl-imx6ul.c163 DeviceState *gic; in fsl_imx6ul_realize() local
184 gic = mpcore; in fsl_imx6ul_realize()
185 gicsbd = SYS_BUS_DEVICE(gic); in fsl_imx6ul_realize()
249 qdev_get_gpio_in(gic, FSL_IMX6UL_GPTn_IRQ[i])); in fsl_imx6ul_realize()
273 qdev_get_gpio_in(gic, FSL_IMX6UL_EPITn_IRQ[i])); in fsl_imx6ul_realize()
310 qdev_get_gpio_in(gic, FSL_IMX6UL_GPIOn_LOW_IRQ[i])); in fsl_imx6ul_realize()
313 qdev_get_gpio_in(gic, FSL_IMX6UL_GPIOn_HIGH_IRQ[i])); in fsl_imx6ul_realize()
367 qdev_get_gpio_in(gic, FSL_IMX6UL_SPIn_IRQ[i])); in fsl_imx6ul_realize()
392 qdev_get_gpio_in(gic, FSL_IMX6UL_I2Cn_IRQ[i])); in fsl_imx6ul_realize()
429 qdev_get_gpio_in(gic, FSL_IMX6UL_UARTn_IRQ[i])); in fsl_imx6ul_realize()
[all …]
H A Dnpcm8xx.c402 return qdev_get_gpio_in(DEVICE(&s->gic), n); in npcm8xx_irq()
416 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); in npcm8xx_init()
504 object_property_set_uint(OBJECT(&s->gic), "num-cpu", nc->num_cpus, errp); in npcm8xx_realize()
505 object_property_set_uint(OBJECT(&s->gic), "num-irq", NPCM8XX_NUM_IRQ, errp); in npcm8xx_realize()
506 object_property_set_uint(OBJECT(&s->gic), "revision", 2, errp); in npcm8xx_realize()
507 object_property_set_bool(OBJECT(&s->gic), "has-security-extensions", true, in npcm8xx_realize()
509 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { in npcm8xx_realize()
513 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, in npcm8xx_realize()
515 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus, in npcm8xx_realize()
517 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus * 2, in npcm8xx_realize()
[all …]
H A Dmps3r.c105 GICv3State gic; member
268 object_initialize_child(OBJECT(mms), "gic", &mms->gic, TYPE_ARM_GICV3); in create_gic()
269 gicdev = DEVICE(&mms->gic); in create_gic()
275 object_property_set_link(OBJECT(&mms->gic), "sysmem", in create_gic()
277 sysbus_realize(SYS_BUS_DEVICE(&mms->gic), &error_fatal); in create_gic()
278 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 0, PERIPHBASE); in create_gic()
279 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 1, PERIPHBASE + 0x100000); in create_gic()
287 SysBusDevice *gicsbd = SYS_BUS_DEVICE(&mms->gic); in create_gic()
406 gicdev = DEVICE(&mms->gic); in mps3r_common_init()
H A Dvirt.c701 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq)); in create_acpi_ged()
724 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic), in create_its()
747 qdev_get_gpio_in(vms->gic, irq + i)); in create_v2m()
798 vms->gic = qdev_new(gictype); in create_gic()
799 qdev_prop_set_uint32(vms->gic, "revision", revision); in create_gic()
800 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); in create_gic()
804 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); in create_gic()
806 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure); in create_gic()
825 qdev_prop_set_array(vms->gic, "redist-region-count", in create_gic()
830 object_property_set_link(OBJECT(vms->gic), "sysmem", in create_gic()
[all …]
/qemu/include/hw/timer/
H A Dmips_gictimer.h34 uint32_t mips_gictimer_get_freq(MIPSGICTimerState *gic);
35 uint32_t mips_gictimer_get_sh_count(MIPSGICTimerState *gic);
36 void mips_gictimer_store_sh_count(MIPSGICTimerState *gic, uint64_t count);
39 void mips_gictimer_store_vp_compare(MIPSGICTimerState *gic, uint32_t vp_index,
41 uint8_t mips_gictimer_get_countstop(MIPSGICTimerState *gic);
42 void mips_gictimer_start_count(MIPSGICTimerState *gic);
43 void mips_gictimer_stop_count(MIPSGICTimerState *gic);
/qemu/hw/cpu/
H A Drealview_mpcore.c33 RealViewGICState gic[4]; member
65 DeviceState *gic; in realview_mpcore_realize() local
79 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic[n]), errp)) { in realview_mpcore_realize()
82 gic = DEVICE(&s->gic[n]); in realview_mpcore_realize()
83 gicbusdev = SYS_BUS_DEVICE(&s->gic[n]); in realview_mpcore_realize()
87 s->rvic[n][i] = qdev_get_gpio_in(gic, i); in realview_mpcore_realize()
106 object_initialize_child(obj, "gic[*]", &s->gic[i], TYPE_REALVIEW_GIC); in mpcore_rirq_init()
H A Darm11mpcore.c24 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in mpcore_priv_set_irq()
31 DeviceState *gicdev = DEVICE(&s->gic); in mpcore_priv_map_setup()
32 SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic); in mpcore_priv_map_setup()
76 DeviceState *gicdev = DEVICE(&s->gic); in mpcore_priv_realize()
91 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { in mpcore_priv_realize()
96 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic)); in mpcore_priv_realize()
125 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); in mpcore_priv_initfn()
127 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0); in mpcore_priv_initfn()
H A Da15mpcore.c35 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in a15mp_priv_set_irq()
46 object_initialize_child(obj, "gic", &s->gic, gic_class_name()); in a15mp_priv_initfn()
47 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); in a15mp_priv_initfn()
66 gicdev = DEVICE(&s->gic); in a15mp_priv_realize()
84 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { in a15mp_priv_realize()
87 busdev = SYS_BUS_DEVICE(&s->gic); in a15mp_priv_realize()
H A Da9mpcore.c26 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in a9mp_priv_set_irq()
38 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); in a9mp_priv_initfn()
80 gicdev = DEVICE(&s->gic); in a9mp_priv_realize()
93 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { in a9mp_priv_realize()
96 gicbusdev = SYS_BUS_DEVICE(&s->gic); in a9mp_priv_realize()
/qemu/hw/mips/
H A Dcps.c33 return s->gic.irq_state[pin_number].irq; in get_cps_irq()
135 object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC); in mips_cps_realize()
136 object_property_set_uint(OBJECT(&s->gic), "num-vp", s->num_vp, in mips_cps_realize()
138 object_property_set_uint(OBJECT(&s->gic), "num-irq", 128, in mips_cps_realize()
140 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { in mips_cps_realize()
145 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0)); in mips_cps_realize()
157 object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr), in mips_cps_realize()
/qemu/hw/vmapple/
H A Dvmapple.c62 DeviceState *gic; member
214 sysbus_connect_irq(gfx, 0, qdev_get_gpio_in(vms->gic, irq_gfx)); in create_gfx()
215 sysbus_connect_irq(gfx, 1, qdev_get_gpio_in(vms->gic, irq_iosfc)); in create_gfx()
227 sysbus_connect_irq(aes, 0, qdev_get_gpio_in(vms->gic, irq)); in create_aes()
245 vms->gic = qdev_new(gicv3_class_name()); in create_gic()
246 qdev_prop_set_uint32(vms->gic, "revision", 3); in create_gic()
247 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); in create_gic()
252 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); in create_gic()
260 qdev_prop_set_array(vms->gic, "redist-region-count", redist_region_count); in create_gic()
262 gicbusdev = SYS_BUS_DEVICE(vms->gic); in create_gic()
[all …]
/qemu/qapi/
H A Dmisc-arm.json31 # @query-gic-capabilities:
49 { 'command': 'query-gic-capabilities', 'returns': ['GICCapability'] }
/qemu/include/hw/intc/
H A Drealview_gic.h25 GICState gic; member

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