Searched refs:ctr_idx (Results 1 – 5 of 5) sorted by relevance
| /qemu/target/riscv/ |
| H A D | pmu.c | 82 static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) in riscv_pmu_counter_valid() argument
84 if (ctr_idx < 3 || ctr_idx >= RV_MAX_MHPMCOUNTERS || in riscv_pmu_counter_valid()
85 !(cpu->pmu_avail_ctrs & BIT(ctr_idx))) { in riscv_pmu_counter_valid()
92 static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, uint32_t ctr_idx) in riscv_pmu_counter_enabled() argument
96 if (riscv_pmu_counter_valid(cpu, ctr_idx) && in riscv_pmu_counter_enabled()
97 !get_field(env->mcountinhibit, BIT(ctr_idx))) { in riscv_pmu_counter_enabled()
104 static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx) in riscv_pmu_incr_ctr_rv32() argument
108 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; in riscv_pmu_incr_ctr_rv32()
113 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) || in riscv_pmu_incr_ctr_rv32()
115 (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VSINH)) || in riscv_pmu_incr_ctr_rv32()
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| H A D | pmu.h | 32 uint32_t ctr_idx);
36 uint32_t ctr_idx);
40 bool upper_half, uint32_t ctr_idx);
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| H A D | csr.c | 1300 uint32_t ctr_idx) in riscv_pmu_write_ctr() argument
1302 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; in riscv_pmu_write_ctr()
1306 if (!get_field(env->mcountinhibit, BIT(ctr_idx)) && in riscv_pmu_write_ctr()
1307 (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || in riscv_pmu_write_ctr()
1308 riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) { in riscv_pmu_write_ctr()
1310 ctr_idx, false); in riscv_pmu_write_ctr()
1311 if (ctr_idx > 2) { in riscv_pmu_write_ctr()
1316 riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); in riscv_pmu_write_ctr()
1327 uint32_t ctr_idx) in riscv_pmu_write_ctrh() argument
1329 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; in riscv_pmu_write_ctrh()
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| /qemu/hw/riscv/ |
| H A D | riscv-iommu-hpm.c | 58 static void hpm_incr_ctr(RISCVIOMMUState *s, uint32_t ctr_idx) in hpm_incr_ctr() argument
60 const uint32_t off = ctr_idx << 3; in hpm_incr_ctr()
76 BIT(ctr_idx + 1), 0); in hpm_incr_ctr()
77 if (!get_field(ovf, BIT(ctr_idx + 1))) { in hpm_incr_ctr()
94 uint32_t ctr_idx; in riscv_iommu_hpm_incr_ctr() local
110 ctr_idx = ctz32(ctrs); in riscv_iommu_hpm_incr_ctr()
111 if (get_field(inhibit, BIT(ctr_idx + 1))) { in riscv_iommu_hpm_incr_ctr()
116 RISCV_IOMMU_REG_IOHPMEVT_BASE + (ctr_idx << 3)); in riscv_iommu_hpm_incr_ctr()
170 hpm_incr_ctr(s, ctr_idx); in riscv_iommu_hpm_incr_ctr()
313 uint32_t ctr_idx) in update_event_map() argument
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| H A D | trace-events | 26 riscv_iommu_hpm_evt_write(uint32_t ctr_idx, uint32_t ovf, uint64_t val) "ctr_idx 0x%x ovf 0x%x val …
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