82 static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx)  in riscv_pmu_counter_valid()  argument
84     if (ctr_idx < 3 || ctr_idx >= RV_MAX_MHPMCOUNTERS ||  in riscv_pmu_counter_valid()
85         !(cpu->pmu_avail_ctrs & BIT(ctr_idx))) {  in riscv_pmu_counter_valid()
92 static bool riscv_pmu_counter_enabled(RISCVCPU *cpu, uint32_t ctr_idx)  in riscv_pmu_counter_enabled()  argument
96     if (riscv_pmu_counter_valid(cpu, ctr_idx) &&  in riscv_pmu_counter_enabled()
97         !get_field(env->mcountinhibit, BIT(ctr_idx))) {  in riscv_pmu_counter_enabled()
104 static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx)  in riscv_pmu_incr_ctr_rv32()  argument
108     PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];  in riscv_pmu_incr_ctr_rv32()
113         (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) ||  in riscv_pmu_incr_ctr_rv32()
115         (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VSINH)) ||  in riscv_pmu_incr_ctr_rv32()
117         (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VUINH)) ||  in riscv_pmu_incr_ctr_rv32()
119         (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_SINH)) ||  in riscv_pmu_incr_ctr_rv32()
121         (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_UINH))) {  in riscv_pmu_incr_ctr_rv32()
131             if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) {  in riscv_pmu_incr_ctr_rv32()
132                 env->mhpmeventh_val[ctr_idx] |= MHPMEVENTH_BIT_OF;  in riscv_pmu_incr_ctr_rv32()
145 static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t ctr_idx)  in riscv_pmu_incr_ctr_rv64()  argument
148     PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];  in riscv_pmu_incr_ctr_rv64()
154         (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) ||  in riscv_pmu_incr_ctr_rv64()
156         (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VSINH)) ||  in riscv_pmu_incr_ctr_rv64()
158         (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VUINH)) ||  in riscv_pmu_incr_ctr_rv64()
160         (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) ||  in riscv_pmu_incr_ctr_rv64()
162         (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) {  in riscv_pmu_incr_ctr_rv64()
170         if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) {  in riscv_pmu_incr_ctr_rv64()
171             env->mhpmevent_val[ctr_idx] |= MHPMEVENT_BIT_OF;  in riscv_pmu_incr_ctr_rv64()
277     uint32_t ctr_idx;  in riscv_pmu_incr_ctr()  local
291     ctr_idx = GPOINTER_TO_UINT(value);  in riscv_pmu_incr_ctr()
292     if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) {  in riscv_pmu_incr_ctr()
297         ret = riscv_pmu_incr_ctr_rv32(cpu, ctr_idx);  in riscv_pmu_incr_ctr()
299         ret = riscv_pmu_incr_ctr_rv64(cpu, ctr_idx);  in riscv_pmu_incr_ctr()
310     uint32_t ctr_idx;  in riscv_pmu_ctr_monitor_instructions()  local
323     ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,  in riscv_pmu_ctr_monitor_instructions()
325     if (!ctr_idx) {  in riscv_pmu_ctr_monitor_instructions()
329     return target_ctr == ctr_idx ? true : false;  in riscv_pmu_ctr_monitor_instructions()
336     uint32_t ctr_idx;  in riscv_pmu_ctr_monitor_cycles()  local
349     ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,  in riscv_pmu_ctr_monitor_cycles()
353     if (!ctr_idx) {  in riscv_pmu_ctr_monitor_cycles()
357     return (target_ctr == ctr_idx) ? true : false;  in riscv_pmu_ctr_monitor_cycles()
380                                uint32_t ctr_idx)  in riscv_pmu_update_event_map()  argument
385     if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map) {  in riscv_pmu_update_event_map()
396                                     GUINT_TO_POINTER(ctr_idx));  in riscv_pmu_update_event_map()
418                         GUINT_TO_POINTER(ctr_idx));  in riscv_pmu_update_event_map()
423 static bool pmu_hpmevent_is_of_set(CPURISCVState *env, uint32_t ctr_idx)  in pmu_hpmevent_is_of_set()  argument
429         mhpmevent_val = env->mhpmeventh_val[ctr_idx];  in pmu_hpmevent_is_of_set()
432         mhpmevent_val = env->mhpmevent_val[ctr_idx];  in pmu_hpmevent_is_of_set()
439 static bool pmu_hpmevent_set_of_if_clear(CPURISCVState *env, uint32_t ctr_idx)  in pmu_hpmevent_set_of_if_clear()  argument
445         mhpmevent_val = &env->mhpmeventh_val[ctr_idx];  in pmu_hpmevent_set_of_if_clear()
448         mhpmevent_val = &env->mhpmevent_val[ctr_idx];  in pmu_hpmevent_set_of_if_clear()
463     uint32_t ctr_idx;  in pmu_timer_trigger_irq()  local
475     ctr_idx = GPOINTER_TO_UINT(g_hash_table_lookup(cpu->pmu_event_ctr_map,  in pmu_timer_trigger_irq()
477     if (!riscv_pmu_counter_enabled(cpu, ctr_idx)) {  in pmu_timer_trigger_irq()
482     if (pmu_hpmevent_is_of_set(env, ctr_idx)) {  in pmu_timer_trigger_irq()
486     counter = &env->pmu_ctrs[ctr_idx];  in pmu_timer_trigger_irq()
495     riscv_pmu_read_ctr(env, (target_ulong *)&curr_ctr_val, false, ctr_idx);  in pmu_timer_trigger_irq()
498         riscv_pmu_read_ctr(env, (target_ulong *)&curr_ctrh_val, true, ctr_idx);  in pmu_timer_trigger_irq()
511         riscv_pmu_setup_timer(env, curr_ctr_val, ctr_idx);  in pmu_timer_trigger_irq()
515     if (cpu->pmu_avail_ctrs & BIT(ctr_idx)) {  in pmu_timer_trigger_irq()
516         if (pmu_hpmevent_set_of_if_clear(env, ctr_idx)) {  in pmu_timer_trigger_irq()
532 int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx)  in riscv_pmu_setup_timer()  argument
537     PMUCTRState *counter = &env->pmu_ctrs[ctr_idx];  in riscv_pmu_setup_timer()
540     if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf ||  in riscv_pmu_setup_timer()
541         pmu_hpmevent_is_of_set(env, ctr_idx)) {  in riscv_pmu_setup_timer()
560     if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||  in riscv_pmu_setup_timer()
561         riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {  in riscv_pmu_setup_timer()