58 static void hpm_incr_ctr(RISCVIOMMUState *s, uint32_t ctr_idx)  in hpm_incr_ctr()  argument
60     const uint32_t off = ctr_idx << 3;  in hpm_incr_ctr()
76                                   BIT(ctr_idx + 1), 0);  in hpm_incr_ctr()
77         if (!get_field(ovf, BIT(ctr_idx + 1))) {  in hpm_incr_ctr()
94     uint32_t ctr_idx;  in riscv_iommu_hpm_incr_ctr()  local
110         ctr_idx = ctz32(ctrs);  in riscv_iommu_hpm_incr_ctr()
111         if (get_field(inhibit, BIT(ctr_idx + 1))) {  in riscv_iommu_hpm_incr_ctr()
116             RISCV_IOMMU_REG_IOHPMEVT_BASE + (ctr_idx << 3));  in riscv_iommu_hpm_incr_ctr()
170         hpm_incr_ctr(s, ctr_idx);  in riscv_iommu_hpm_incr_ctr()
313                              uint32_t ctr_idx)  in update_event_map()  argument
316     uint32_t pair[2] = { ctr_idx, RISCV_IOMMU_HPMEVENT_INVALID };  in update_event_map()
317     uint32_t new_value = 1 << ctr_idx;  in update_event_map()
355     const uint32_t ctr_idx = (evt_reg - RISCV_IOMMU_REG_IOHPMEVT_BASE) >> 3;  in riscv_iommu_process_hpmevt_write()  local
359     if (ctr_idx >= s->hpm_cntrs) {  in riscv_iommu_process_hpmevt_write()
363     trace_riscv_iommu_hpm_evt_write(ctr_idx, ovf, val);  in riscv_iommu_process_hpmevt_write()
366     if (get_field(ovf, BIT(ctr_idx + 1)) &&  in riscv_iommu_process_hpmevt_write()
370             s, RISCV_IOMMU_REG_IOCOUNTOVF, 0, BIT(ctr_idx + 1));  in riscv_iommu_process_hpmevt_write()
380     update_event_map(s, val, ctr_idx);  in riscv_iommu_process_hpmevt_write()