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Searched refs:cr1 (Results 1 – 6 of 6) sorted by relevance

/qemu/tests/qtest/
H A Dstm32l4x5_usart-test.c175 uint32_t cr1; in init_uart() local
191 cr1 = qtest_readl(qts, (USART1_BASE_ADDR + A_CR1)); in init_uart()
192 cr1 &= ~(R_CR1_M1_MASK | R_CR1_M0_MASK | R_CR1_OVER8_MASK | R_CR1_PCE_MASK); in init_uart()
193 qtest_writel(qts, (USART1_BASE_ADDR + A_CR1), cr1); in init_uart()
197 cr1 | R_CR1_UE_MASK | R_CR1_RE_MASK | R_CR1_TE_MASK); in init_uart()
215 uint32_t cr1; in test_receive_char() local
227 cr1 = qtest_readl(qts, (USART1_BASE_ADDR + A_CR1)); in test_receive_char()
228 cr1 |= R_CR1_RXNEIE_MASK; in test_receive_char()
229 qtest_writel(qts, USART1_BASE_ADDR + A_CR1, cr1); in test_receive_char()
245 uint32_t cr1; in test_send_char() local
[all …]
/qemu/hw/char/
H A Dstm32l4x5_usart.c159 if (s->cr1 & R_CR1_TE_MASK) { in stm32l4x5_update_isr()
165 if (s->cr1 & R_CR1_RE_MASK) { in stm32l4x5_update_isr()
175 ((s->isr & R_ISR_CMF_MASK) && (s->cr1 & R_CR1_CMIE_MASK)) || in stm32l4x5_update_irq()
176 ((s->isr & R_ISR_ABRF_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || in stm32l4x5_update_irq()
177 ((s->isr & R_ISR_EOBF_MASK) && (s->cr1 & R_CR1_EOBIE_MASK)) || in stm32l4x5_update_irq()
178 ((s->isr & R_ISR_RTOF_MASK) && (s->cr1 & R_CR1_RTOIE_MASK)) || in stm32l4x5_update_irq()
181 ((s->isr & R_ISR_TXE_MASK) && (s->cr1 & R_CR1_TXEIE_MASK)) || in stm32l4x5_update_irq()
182 ((s->isr & R_ISR_TC_MASK) && (s->cr1 & R_CR1_TCIE_MASK)) || in stm32l4x5_update_irq()
183 ((s->isr & R_ISR_RXNE_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || in stm32l4x5_update_irq()
184 ((s->isr & R_ISR_IDLE_MASK) && (s->cr1 & R_CR1_IDLEIE_MASK)) || in stm32l4x5_update_irq()
[all …]
/qemu/hw/ssi/
H A Dpl022.c79 if ((s->cr1 & PL022_CR1_SSE) == 0) { in pl022_xfer()
103 if (s->cr1 & PL022_CR1_LBM) { in pl022_xfer()
131 return s->cr1; in pl022_read()
174 s->cr1 = value; in pl022_write()
175 if ((s->cr1 & (PL022_CR1_MS | PL022_CR1_SSE)) in pl022_write()
254 VMSTATE_UINT32(cr1, PL022State),
/qemu/include/hw/ssi/
H A Dpl022.h36 uint32_t cr1; member
/qemu/include/hw/char/
H A Dstm32l4x5_usart.h43 uint32_t cr1; member
/qemu/hw/net/
H A Dcadence_gem.c912 uint32_t cr0, cr1, mask, compare, disable_mask; in get_queue_from_screen() local
929 cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_1 + cr_idx * 2]; in get_queue_from_screen()
930 offset = FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE); in get_queue_from_screen()
932 switch (FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET)) { in get_queue_from_screen()
950 FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, DISABLE_MASK); in get_queue_from_screen()