Lines Matching refs:cr1
159 if (s->cr1 & R_CR1_TE_MASK) { in stm32l4x5_update_isr()
165 if (s->cr1 & R_CR1_RE_MASK) { in stm32l4x5_update_isr()
175 ((s->isr & R_ISR_CMF_MASK) && (s->cr1 & R_CR1_CMIE_MASK)) || in stm32l4x5_update_irq()
176 ((s->isr & R_ISR_ABRF_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || in stm32l4x5_update_irq()
177 ((s->isr & R_ISR_EOBF_MASK) && (s->cr1 & R_CR1_EOBIE_MASK)) || in stm32l4x5_update_irq()
178 ((s->isr & R_ISR_RTOF_MASK) && (s->cr1 & R_CR1_RTOIE_MASK)) || in stm32l4x5_update_irq()
181 ((s->isr & R_ISR_TXE_MASK) && (s->cr1 & R_CR1_TXEIE_MASK)) || in stm32l4x5_update_irq()
182 ((s->isr & R_ISR_TC_MASK) && (s->cr1 & R_CR1_TCIE_MASK)) || in stm32l4x5_update_irq()
183 ((s->isr & R_ISR_RXNE_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || in stm32l4x5_update_irq()
184 ((s->isr & R_ISR_IDLE_MASK) && (s->cr1 & R_CR1_IDLEIE_MASK)) || in stm32l4x5_update_irq()
186 ((s->cr1 & R_CR1_RXNEIE_MASK) || (s->cr3 & R_CR3_EIE_MASK))) || in stm32l4x5_update_irq()
189 ((s->isr & R_ISR_PE_MASK) && (s->cr1 & R_CR1_PEIE_MASK))) { in stm32l4x5_update_irq()
214 if (!((s->cr1 & R_CR1_UE_MASK) && (s->cr1 & R_CR1_RE_MASK))) { in stm32l4x5_usart_base_receive()
216 FIELD_EX32(s->cr1, CR1, UE), FIELD_EX32(s->cr1, CR1, RE)); in stm32l4x5_usart_base_receive()
252 if (!(s->cr1 & R_CR1_TE_MASK) || (s->isr & R_ISR_TXE_MASK)) { in usart_transmit()
296 if (s->cr1 & R_CR1_PCE_MASK) { in stm32l4x5_update_params()
297 if (s->cr1 & R_CR1_PS_MASK) { in stm32l4x5_update_params()
322 switch ((FIELD_EX32(s->cr1, CR1, M1) << 1) | FIELD_EX32(s->cr1, CR1, M0)) { in stm32l4x5_update_params()
346 if (FIELD_EX32(s->cr1, CR1, OVER8) == 0) { in stm32l4x5_update_params()
379 s->cr1 = 0x00000000; in stm32l4x5_usart_base_reset_hold()
414 retvalue = s->cr1; in stm32l4x5_usart_base_read()
472 s->cr1 = value; in stm32l4x5_usart_base_write()
568 VMSTATE_UINT32(cr1, Stm32l4x5UsartBaseState),