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Searched refs:TM_QW1_OS (Results 1 – 6 of 6) sorted by relevance

/qemu/hw/intc/
H A Dxive2.c622 for (cur_ring = TM_QW1_OS; cur_ring <= ring; in xive2_tm_pull_ctx()
632 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW1_OS); in xive2_tm_pull_os_ctx()
652 data[0x4] = regs[TM_QW1_OS + TM_ACK_CNT]; in xive2_tm_report_line_gen1()
657 data[0x7] |= (regs[TM_QW1_OS + TM_WORD2] & 0x80) >> 2; in xive2_tm_report_line_gen1()
659 data[0x8] = regs[TM_QW1_OS + TM_NSR]; in xive2_tm_report_line_gen1()
660 data[0x9] = regs[TM_QW1_OS + TM_CPPR]; in xive2_tm_report_line_gen1()
661 data[0xA] = regs[TM_QW1_OS + TM_IPB]; in xive2_tm_report_line_gen1()
662 data[0xB] = regs[TM_QW1_OS + TM_LGS]; in xive2_tm_report_line_gen1()
734 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW1_OS); in xive2_tm_pull_os_ctx_ol()
762 tctx->regs[TM_QW1_OS + TM_CPPR] = cppr; in xive2_tctx_restore_os_ctx()
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H A Dxive.c34 case TM_QW1_OS: in xive_tctx_output()
96 case TM_QW1_OS: in xive_tctx_notify()
384 return xive_tctx_accept(tctx, TM_QW1_OS); in xive_tm_ack_os_reg()
390 xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); in xive_tm_set_os_cppr()
403 xive_tctx_set_lgs(tctx, TM_QW1_OS, value & 0xff); in xive_tm_set_os_lgs()
413 xive_tctx_pipr_update(tctx, TM_QW1_OS, value & 0xff, 0); in xive_tm_set_os_pending()
433 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); in xive_tctx_get_os_cam()
442 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); in xive_tctx_set_os_cam()
465 xive_tctx_reset_signal(tctx, TM_QW1_OS); in xive_tm_pull_os_ctx()
492 uint8_t *regs = &tctx->regs[TM_QW1_OS]; in xive_tctx_need_resend()
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H A Dspapr_xive_kvm.c86 state[0] = *((uint64_t *) &tctx->regs[TM_QW1_OS]); in kvmppc_xive_cpu_set_state()
116 *((uint64_t *) &tctx->regs[TM_QW1_OS]) = state[0]; in kvmppc_xive_cpu_get_state()
H A Dspapr_xive.c657 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); in xive_tctx_set_os_cam()
/qemu/tests/qtest/
H A Dpnv-xive2-test.c365 qw1w0 = get_tima32(qts, target_pir, TM_QW1_OS + TM_WORD0); in test_pull_thread_ctx_to_odd_thread_cl()
367 qw1w2 = get_tima32(qts, target_pir, TM_QW1_OS + TM_WORD2); in test_pull_thread_ctx_to_odd_thread_cl()
376 memcpy(&cl_word, &cl_pair[XIVE_ODD_CL + TM_QW1_OS + TM_WORD0], 4); in test_pull_thread_ctx_to_odd_thread_cl()
380 memcpy(&cl_word, &cl_pair[XIVE_ODD_CL + TM_QW1_OS + TM_WORD2], 4); in test_pull_thread_ctx_to_odd_thread_cl()
388 word2 = get_tima32(qts, target_pir, TM_QW1_OS + TM_WORD2); in test_pull_thread_ctx_to_odd_thread_cl()
/qemu/include/hw/ppc/
H A Dxive_regs.h68 #define TM_QW1_OS 0x010 /* Ring 0..2 */ macro