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Searched refs:ST (Results 1 – 25 of 27) sorted by relevance

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/qemu/target/arm/tcg/
H A Dsve_ldst_internal.h93 #define DO_ST_PRIM_2(NAME, H, TE, TM, ST) \ argument
94 DO_ST_HOST(st1##NAME##_be, H, TE, TM, ST##_be_p) \
95 DO_ST_HOST(st1##NAME##_le, H, TE, TM, ST##_le_p) \
96 DO_ST_TLB(st1##NAME##_be, H, TE, TM, cpu_##ST##_be_data_ra) \
97 DO_ST_TLB(st1##NAME##_le, H, TE, TM, cpu_##ST##_le_data_ra)
H A Dsve_helper.c5063 #define DO_FCMGE(TYPE, X, Y, ST) TYPE##_compare(Y, X, ST) <= 0 argument
5064 #define DO_FCMGT(TYPE, X, Y, ST) TYPE##_compare(Y, X, ST) < 0 argument
5065 #define DO_FCMLE(TYPE, X, Y, ST) TYPE##_compare(X, Y, ST) <= 0 argument
5066 #define DO_FCMLT(TYPE, X, Y, ST) TYPE##_compare(X, Y, ST) < 0 argument
5067 #define DO_FCMEQ(TYPE, X, Y, ST) TYPE##_compare_quiet(X, Y, ST) == 0 argument
5068 #define DO_FCMNE(TYPE, X, Y, ST) TYPE##_compare_quiet(X, Y, ST) != 0 argument
5069 #define DO_FCMUO(TYPE, X, Y, ST) \ argument
5070 TYPE##_compare_quiet(X, Y, ST) == float_relation_unordered
5071 #define DO_FACGE(TYPE, X, Y, ST) \ argument
5072 TYPE##_compare(TYPE##_abs(Y), TYPE##_abs(X), ST) <= 0
[all …]
H A Dtranslate-mve.c203 #define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \ argument
207 { gen_helper_mve_##ST, gen_helper_mve_##SLD }, \
H A Dcpu64.c1233 t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ in aarch64_max_tcg_initfn()
/qemu/tests/tcg/i386/
H A Dx86.csv585 "FADD ST(i), ST(0)","FADDD ST(0), ST(i)","fadd ST(0), ST(i)","DC C0+i","V","V","","","rw,r","Y",""
586 "FADD ST(0), ST(i)","FADDD ST(i), ST(0)","fadd ST(i), ST(0)","D8 C0+i","V","V","","","rw,r","Y",""
587 "FADD ST(0), m32fp","FADDD m32fp, ST(0)","fadds m32fp, ST(0)","D8 /0","V","V","","","rw,r","Y","32"
588 "FADD ST(0), m64fp","FADDD m64fp, ST(0)","faddl m64fp, ST(0)","DC /0","V","V","","","rw,r","Y","64"
590 "FADDP ST(i), ST(0)","FADDDP ST(0), ST(i)","faddp ST(0), ST(i)","DE C0+i","V","V","","","rw,r","",""
591 "FBLD ST(0), m80dec","FBLD m80dec, ST(0)","fbld m80dec, ST(0)","DF /4","V","V","","","w,r","",""
592 "FBSTP m80dec, ST(0)","FBSTP ST(0), m80dec","fbstp ST(0), m80dec","DF /6","V","V","","","w,r","",""
595 "FCMOVB ST(0), ST(i)","FCMOVB ST(i), ST(0)","fcmovb ST(i), ST(0)","DA C0+i","V","V","","P6","rw,r",…
596 "FCMOVBE ST(0), ST(i)","FCMOVBE ST(i), ST(0)","fcmovbe ST(i), ST(0)","DA D0+i","V","V","","P6","rw,…
597 "FCMOVE ST(0), ST(i)","FCMOVE ST(i), ST(0)","fcmove ST(i), ST(0)","DA C8+i","V","V","","P6","rw,r",…
[all …]
/qemu/target/i386/tcg/
H A Dfpu_helper.c35 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) macro
36 #define ST1 ST(1)
502 FT0 = ST(st_index); in helper_fmov_FT0_STN()
507 ST0 = ST(st_index); in helper_fmov_ST0_STN()
512 ST(st_index) = ST0; in helper_fmov_STN_ST0()
519 tmp = ST(st_index); in helper_fxchg_ST0_STN()
520 ST(st_index) = ST0; in helper_fxchg_ST0_STN()
619 ST(st_index) = floatx80_add(ST(st_index), ST0, &env->fp_status); in helper_fadd_STN_ST0()
626 ST(st_inde in helper_fmul_STN_ST0()
[all...]
/qemu/include/fpu/
H A Dsoftfloat-types.h249 FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */
/qemu/target/hexagon/imported/
H A Diclass.def29 DEF_PP_ICLASS32(ST,01,LDST) /* 10 */
H A Dencode_pp.def65 /* V2 PREDICATED LD/ST */
121 /* V2 GP-RELATIVE LD/ST */
420 DEF_CLASS32(ICLASS_ST" ---- -------- PP------ --------",ST)
H A Dldst.idef345 /* V2 GP-relative LD/ST */
/qemu/docs/system/
H A Dauthz.rst215 CN=laptop.berrange.com,O=Berrange Home,L=London,ST=London,C=GB
253 echo "CN=laptop.qemu.org,O=QEMU Project,L=London,ST=London,C=GB" >> tls.acl
/qemu/target/mips/tcg/
H A Dmsa.decode258 ST 011110 .......... ..... ..... 1001 .. @ldst
H A Dmsa_translate.c779 TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st);
H A Dmicromips_translate.c.inc371 /* POOL32C ST-EVA encoding of minor opcode field (bits 11..9) */
/qemu/target/xtensa/
H A Dxtensa-isa.c1426 #define CHECK_STATE(INTISA, ST, ERRVAL) \ argument
1428 if ((ST) < 0 || (ST) >= (INTISA)->num_states) { \
/qemu/target/hexagon/
H A Dattribs_def.h.inc166 DEF_ATTRIB(NOTE_NVSLOT0, "Can execute only in slot 0 (ST)", "", "")
/qemu/docs/system/arm/
H A Demulation.rst192 - ST (System Timer Extension)
/qemu/target/sh4/
H A Dtranslate.c1414 #define ST(reg,stnum,stpnum,prechk) \ in _decode_opc() macro
1431 ST(reg,stnum,stpnum,prechk) in _decode_opc()
1436 ST(sgr, 0x003a, 0x4032, CHECK_PRIVILEGED) in _decode_opc()
/qemu/docs/tools/
H A Dqemu-nbd.rst245 O=Example Org,,L=London,,ST=London,,C=GB' \
/qemu/target/arm/
H A Dcpu-features.h848 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; in isar_feature_aa64_st()
H A Dcpu.h2259 FIELD(ID_AA64MMFR2, ST, 28, 4)
/qemu/hw/net/
H A Dcadence_gem.c201 FIELD(PHYMNTNC, ST, 30, 2)
/qemu/target/ppc/translate/
H A Dvmx-impl.c.inc1677 * AB.BC.CD.DE.EF.FG.GH.HI.IJ.JK.KL.LM.MN.NO.OP.PQ.QR.RS.ST.TU.UV.V
1679 * AB....CD....EF....GH....IJ....KL....MN....OP....QR....ST....UV..
1681 * ..CD....EF....GH....IJ....KL....MN....OP....QR....ST....UV......
/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc1259 /* Otherwise use a pair of LD/ST. */
/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc848 D(0x5000, ST, RX_a, Z, r1_o, a2, 0, 0, st32, 0, 0)

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