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Searched refs:R (Results 1 – 25 of 89) sorted by relevance

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/qemu/target/s390x/tcg/
H A Dinsn-format.h.inc5 F2(RI_a, R(1, 8), I(2,16,16))
6 F2(RI_b, R(1, 8), I(2,16,16))
8 F3(RIE_a, R(1, 8), I(2,16,16), M(3,32))
9 F4(RIE_b, R(1, 8), R(2,12), M(3,32), I(4,16,16))
10 F4(RIE_c, R(1, 8), I(2,32, 8), M(3,12), I(4,16,16))
11 F3(RIE_d, R(1, 8), I(2,16,16), R(3,12))
12 F3(RIE_e, R(1, 8), I(2,16,16), R(3,12))
13 F5(RIE_f, R(1, 8), R(2,12), I(3,16,8), I(4,24,8), I(5,32,8))
14 F3(RIE_g, R(1, 8), I(2,16,16), M(3,12))
15 F2(RIL_a, R(1, 8), I(2,16,32))
[all …]
H A Dcrypto_helper.c22 static uint64_t R(uint64_t x, int c) in R() function
36 return R(x, 28) ^ R(x, 34) ^ R(x, 39); in Sigma0()
40 return R(x, 14) ^ R(x, 18) ^ R(x, 41); in Sigma1()
44 return R(x, 1) ^ R(x, 8) ^ (x >> 7); in sigma0()
48 return R(x, 19) ^ R(x, 61) ^ (x >> 6); in sigma1()
/qemu/target/avr/
H A Dtranslate.c216 static void gen_add_CHf(TCGv R, TCGv Rd, TCGv Rr) in gen_add_CHf() argument
223 tcg_gen_andc_tl(t2, Rd, R); /* t2 = Rd & ~R */ in gen_add_CHf()
224 tcg_gen_andc_tl(t3, Rr, R); /* t3 = Rr & ~R */ in gen_add_CHf()
233 static void gen_add_Vf(TCGv R, TCGv Rd, TCGv Rr) in gen_add_Vf() argument
240 tcg_gen_xor_tl(t1, Rd, R); in gen_add_Vf()
247 static void gen_sub_CHf(TCGv R, TCGv Rd, TCGv Rr) in gen_sub_CHf() argument
256 tcg_gen_and_tl(t3, t3, R); in gen_sub_CHf()
264 static void gen_sub_Vf(TCGv R, TCGv Rd, TCGv Rr) in gen_sub_Vf() argument
271 tcg_gen_xor_tl(t1, Rd, R); in gen_sub_Vf()
278 static void gen_NSf(TCGv R) in gen_NSf() argument
[all …]
/qemu/rust/qemu-api/src/
H A Dcallbacks.rs115 pub unsafe trait FnCall<Args, R = ()>: 'static + Sync + Sized {
169 fn call(a: Args) -> R; in call() argument
176 unsafe impl<Args, R> FnCall<Args, R> for () {
180 fn call(_a: Args) -> R { in call() argument
190 unsafe impl<F, $($args,)* R> FnCall<($($args,)*), R> for F
192 F: 'static + Sync + Sized + Fn($($args, )*) -> R,
197 fn call(a: ($($args,)*)) -> R {
H A Dsysbus.rs122 impl<R: ObjectDeref> SysBusDeviceMethods for R where R::Target: IsA<SysBusDevice> {} implementation
H A Dqdev.rs392 impl<R: ObjectDeref> DeviceMethods for R where R::Target: IsA<DeviceState> {}
388 impl<R: ObjectDeref> DeviceMethods for R where R::Target: IsA<DeviceState> {} global() implementation
H A Dqom.rs772 impl<R: ObjectDeref> ObjectMethods for R where R::Target: IsA<Object> {} implementation
/qemu/pc-bios/
H A Dqemu.rsrc99 $"5556 5557 4E07 A800 0122 5680 5203 5151" /* UVUWN.®.."VÄR.QQ */
100 $"4C9C A8FE 05E1 955D 5051 5080 5183 5282" /* Lú®˛.·ï]PQPÄQÉRÇ */
101 $"5180 5208 5151 5051 5152 5254 3FA9 0000" /* QÄR.QQPQQRRT?©.. */
103 $"4F82 5083 4F01 5050 844F 0152 2EA9 0002" /* OÇPÉO.PPÑO.R.©.. */
111 $"9DFE 02EE 9552 8040 8041 8540 8041 0140" /* ù˛.ÓïRÄ@ÄAÖ@ÄA.@ */
197 $"8552 1151 515A 5551 5152 5456 5E6D 89A6" /* ÖR.QQZUQQRTV^mⶠ*/
199 $"BC00 041B 98C7 C5C3 82C4 02BD 684F 8A52" /* º...ò«≈√ǃ.ΩhOäR */
200 $"0051 8152 0C51 5152 5254 5A67 82A2 BAC6" /* .QÅR.QQRRTZgÇ¢∫∆ */
202 $"91C4 C184 C003 C6A2 5551 9252 0951 5152" /* 냡ѿ.∆¢UQíR∆QQR */
204 $"0003 0A7D C1BC 84BB 04BF 9E8E 6A50 9552" /* ..¬}¡ºÑª.øûéjPïR */
[all …]
/qemu/tests/qtest/
H A Dadm1272-test.c86 uint16_t y = (c.m * value + c.b) * pow(10, c.R); in pmbus_data2direct_mode()
93 uint32_t x = (value / pow(10, c.R) - c.b) / c.m; in pmbus_direct_mode2data()
102 c.R = c.R - 3; in adm1272_millivolts_to_direct()
110 c.R = c.R - 3; in adm1272_direct_to_millivolts()
120 c.R = c.R - 3; in adm1272_milliamps_to_direct()
129 c.R = c.R - 3; in adm1272_direct_to_milliamps()
/qemu/target/microblaze/
H A Dtranslate.c1853 #define R(X) { &cpu_R[X], offsetof(CPUMBState, regs[X]), "r" #X } in mb_tcg_init() macro
1865 R(1), R(2), R(3), R(4), R(5), R(6), R(7), in mb_tcg_init()
1866 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), in mb_tcg_init()
1867 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), in mb_tcg_init()
1868 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), in mb_tcg_init()
1880 #undef R in mb_tcg_init()
/qemu/
H A DMAINTAINERS17 R: Designated reviewer: FullName <address@domain>
68 R: Alex Bennée <alex.bennee@linaro.org>
69 R: Daniel P. Berrangé <berrange@redhat.com>
70 R: Thomas Huth <thuth@redhat.com>
71 R: Markus Armbruster <armbru@redhat.com>
72 R: Philippe Mathieu-Daudé <philmd@linaro.org>
130 R: Jiaxun Yang <jiaxun.yang@flygoat.com>
138 R: Zhao Liu <zhao1.liu@intel.com>
153 R: Paolo Bonzini <pbonzini@redhat.com>
277 R: Aurelien Jarno <aurelien@aurel32.net>
[all …]
/qemu/hw/sensor/
H A Dadm1272.c143 c.R = c.R - 3; in adm1272_millivolts_to_direct()
151 c.R = c.R - 3; in adm1272_direct_to_millivolts()
161 c.R = c.R - 3; in adm1272_milliamps_to_direct()
170 c.R = c.R - 3; in adm1272_direct_to_milliamps()
/qemu/scripts/coccinelle/
H A Dreturn_directly.cocci1 // replace 'R = X; return R;' with 'return X;'
/qemu/scripts/codeconverter/codeconverter/
H A Dregexps.py59 OPTIONAL_PARS = lambda R: OR(S(r'\(\s*', R, r'\s*\)'), R) argument
/qemu/hw/net/
H A Dpcnet.c273 #define PRINT_RMD(R) printf( \ argument
279 (R)->rbadr, \
280 GET_FIELD((R)->status, RMDS, OWN), \
281 GET_FIELD((R)->status, RMDS, ERR), \
282 GET_FIELD((R)->status, RMDS, FRAM), \
283 GET_FIELD((R)->status, RMDS, OFLO), \
284 GET_FIELD((R)->status, RMDS, CRC), \
285 GET_FIELD((R)->status, RMDS, BUFF), \
286 GET_FIELD((R)->status, RMDS, STP), \
287 GET_FIELD((R)->status, RMDS, ENP), \
[all …]
/qemu/target/tricore/
H A Dcsfr.h.inc2 R(ead only) access
5 A|R|E(offset, register, feature introducing reg)
12 R(0xfe18, CPU_ID, TRICORE_FEATURE_13)
13 R(0xfe1c, CORE_ID, TRICORE_FEATURE_161)
H A Dcpu.h49 #define R(ADDR, NAME, FEATURE) uint32_t NAME; macro
53 #undef R
/qemu/include/qemu/
H A Dhost-utils.h811 uint64_t q1, q2, Q, r1, r2, R; in udiv_qrnnd()
818 R = r1 + r2; in udiv_qrnnd()
819 if (R >= d || R < r2) { /* overflow implies R > d */ in udiv_qrnnd()
821 R -= d; in udiv_qrnnd()
823 *r = R; in udiv_qrnnd()
/qemu/hw/display/
H A Dexynos4210_fimd.c377 #define DEF_PIXEL_TO_RGB_A1(N, R, G, B) \ argument
386 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
387 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
388 pixel >>= (R); \
400 #define DEF_PIXEL_TO_RGB_A0(N, R, G, B) \ argument
409 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
410 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
420 #define DEF_PIXEL_TO_RGB_A(N, R, G, B, A) \ argument
429 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
430 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
[all …]
/qemu/target/hexagon/idef-parser/
H A Didef-parser.lex77 "R"{REG_ID_32}"V" {
86 "R"{REG_ID_64}"V" {
/qemu/docs/specs/
H A Drocker.rst39 * Register are (R) read-only, (R/W) read/write, (W) write-only, or (COR) clear
174 DMA_DESC_xxx_BASE_ADDR, offset 0x1000 + (x * 32), 64-bit, (R/W)
175 DMA_DESC_xxx_SIZE, offset 0x1008 + (x * 32), 32-bit, (R/W)
176 DMA_DESC_xxx_HEAD, offset 0x100c + (x * 32), 32-bit, (R/W)
177 DMA_DESC_xxx_TAIL, offset 0x1010 + (x * 32), 32-bit, (R)
179 DMA_DESC_xxx_CREDITS, offset 0x1018 + (x * 32), 32-bit, (R/W)
180 DMA_DESC_xxx_RSVD1, offset 0x101c + (x * 32), 32-bit, (R/W)
324 TEST_REG, offset 0x0010, 32-bit (R/W)
325 TEST_REG64, offset 0x0018, 64-bit (R/W)
326 TEST_IRQ, offset 0x0020, 32-bit (R/W)
[all …]
/qemu/target/hexagon/imported/
H A Dencode_subinsn.def114 /* maybe R=cmpeq ? */
117 /* Add a group of NCJ: if (R.new==#0) jump:hint #r9 */
118 /* Add a group of NCJ: if (R.new!=#0) jump:hint #r9 */
/qemu/tests/keys/
H A Did_rsa2 MIIEowIBAAKCAQEAopAuOlmLV6LVHdFBj8/eeOwI9CqguIJPp7eAQSZvOiB4Ag/R
/qemu/fpu/
H A Dsoftfloat.c588 #define FLOATX80_PARAMS(R) \ argument
590 .frac_size = R == 64 ? 63 : R, \
592 .round_mask = R == 64 ? -1 : (1ull << ((-R - 1) & 63)) - 1
843 #define parts_round_to_int_normal(A, R, C, F) \ argument
844 PARTS_GENERIC_64_128(round_to_int_normal, A)(A, R, C, F)
853 #define parts_round_to_int(A, R, C, S, F) \ argument
854 PARTS_GENERIC_64_128(round_to_int, A)(A, R, C, S, F)
863 #define parts_float_to_sint(P, R, Z, MN, MX, S) \ argument
864 PARTS_GENERIC_64_128(float_to_sint, P)(P, R, Z, MN, MX, S)
873 #define parts_float_to_uint(P, R, Z, M, S) \ argument
[all …]
/qemu/docs/
H A Dmulti-thread-compression.txt59 CPU: Intel(R) Xeon(R) CPU E5-2680 0 @ 2.70GHz

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