Lines Matching refs:R

39 * Register are (R) read-only, (R/W) read/write, (W) write-only, or (COR) clear
174 	DMA_DESC_xxx_BASE_ADDR, offset 0x1000 + (x * 32), 64-bit, (R/W)
175 	DMA_DESC_xxx_SIZE, offset 0x1008 + (x * 32), 32-bit, (R/W)
176 	DMA_DESC_xxx_HEAD, offset 0x100c + (x * 32), 32-bit, (R/W)
177 	DMA_DESC_xxx_TAIL, offset 0x1010 + (x * 32), 32-bit, (R)
179 	DMA_DESC_xxx_CREDITS, offset 0x1018 + (x * 32), 32-bit, (R/W)
180 	DMA_DESC_xxx_RSVD1, offset 0x101c + (x * 32), 32-bit, (R/W)
324 	TEST_REG, offset 0x0010, 32-bit (R/W)
325 	TEST_REG64, offset 0x0018, 64-bit (R/W)
326 	TEST_IRQ, offset 0x0020, 32-bit (R/W)
327 	TEST_DMA_ADDR, offset 0x0028, 64-bit (R/W)
328 	TEST_DMA_SIZE, offset 0x0030, 32-bit (R/W)
329 	TEST_DMA_CTRL, offset 0x0034, 32-bit (R/W)
362 	PORT_PHYS_COUNT, offset 0x0304, 32-bit, (R)
395 	PORT_PHYS_LINK_STATUS, offset 0x0310, 64-bit, (R)
442 	PORT_PHYS_ENABLE: offset 0x0318, 64-bit, (R/W)
472 	SWITCH_ID: offset 0x0320, 64-bit, (R)