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Searched refs:PPC_BITMASK32 (Results 1 – 7 of 7) sorted by relevance

/qemu/include/hw/ppc/
H A Dxive2_regs.h24 #define TM2_QW0W2_LOGIC_SERV PPC_BITMASK32(4, 31)
27 #define TM2_QW1W2_OS_CAM PPC_BITMASK32(4, 31)
30 #define TM2_QW2W2_POOL_CAM PPC_BITMASK32(4, 31)
72 #define END2_W0_AEC_SIZE PPC_BITMASK32(18, 19)
73 #define END2_W0_AEG_SIZE PPC_BITMASK32(20, 23)
74 #define END2_W0_EQ_VG_PREDICT PPC_BITMASK32(24, 31) /* Owned by HW */
76 #define END2_W1_ESn PPC_BITMASK32(0, 1)
79 #define END2_W1_ESe PPC_BITMASK32(2, 3)
84 #define END2_W1_PAGE_OFF PPC_BITMASK32(10, 31)
86 #define END2_W2_RESERVED PPC_BITMASK32(4, 7)
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H A Dxive_regs.h94 #define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1, 31) /* XX 2,31 ? */
96 #define TM_QW1W2_OS_CAM PPC_BITMASK32(8, 31)
98 #define TM_QW2W2_POOL_CAM PPC_BITMASK32(8, 31)
235 #define END_W0_QSIZE PPC_BITMASK32(12, 15)
240 #define END_W0_HWDEP PPC_BITMASK32(24, 31)
242 #define END_W1_ESn PPC_BITMASK32(0, 1)
245 #define END_W1_ESe PPC_BITMASK32(2, 3)
249 #define END_W1_PAGE_OFF PPC_BITMASK32(10, 31)
251 #define END_W2_MIGRATION_REG PPC_BITMASK32(0, 3)
252 #define END_W2_OP_DESC_HI PPC_BITMASK32(4, 31)
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/qemu/tests/qtest/
H A Dpnv-xive2-common.h16 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \ macro
H A Dpnv-host-i2c-test.c19 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \ macro
/qemu/hw/ppc/
H A Dpnv_core.c616 switch (offset & ~PPC_BITMASK32(16, 19)) { in pnv_qme_power10_xscom_read()
640 switch (offset & ~PPC_BITMASK32(16, 19)) { in pnv_qme_power10_xscom_write()
H A Dpnv_lpc.c434 if ((lpc->opb_irq_route0 & PPC_BITMASK32(8, 13)) || in pnv_lpc_eval_serirq_routes()
435 (lpc->opb_irq_route1 & PPC_BITMASK32(4, 31))) { in pnv_lpc_eval_serirq_routes()
/qemu/target/ppc/
H A Dcpu.h49 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \ macro