Lines Matching refs:PPC_BITMASK32
94 #define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1, 31) /* XX 2,31 ? */
96 #define TM_QW1W2_OS_CAM PPC_BITMASK32(8, 31)
98 #define TM_QW2W2_POOL_CAM PPC_BITMASK32(8, 31)
235 #define END_W0_QSIZE PPC_BITMASK32(12, 15)
240 #define END_W0_HWDEP PPC_BITMASK32(24, 31)
242 #define END_W1_ESn PPC_BITMASK32(0, 1)
245 #define END_W1_ESe PPC_BITMASK32(2, 3)
249 #define END_W1_PAGE_OFF PPC_BITMASK32(10, 31)
251 #define END_W2_MIGRATION_REG PPC_BITMASK32(0, 3)
252 #define END_W2_OP_DESC_HI PPC_BITMASK32(4, 31)
254 #define END_W3_OP_DESC_LO PPC_BITMASK32(0, 31)
256 #define END_W4_ESC_END_BLOCK PPC_BITMASK32(4, 7)
257 #define END_W4_ESC_END_INDEX PPC_BITMASK32(8, 31)
259 #define END_W5_ESC_END_DATA PPC_BITMASK32(1, 31)
262 #define END_W6_NVT_BLOCK PPC_BITMASK32(9, 12)
263 #define END_W6_NVT_INDEX PPC_BITMASK32(13, 31)
267 #define END_W7_F0_PRIORITY PPC_BITMASK32(8, 15)
269 #define END_W7_F1_LOG_SERVER_ID PPC_BITMASK32(1, 31)
299 #define NVT_W1_EQ_BLOCK PPC_BITMASK32(0, 3)
300 #define NVT_W1_EQ_INDEX PPC_BITMASK32(4, 31)
304 #define NVT_W4_IPB PPC_BITMASK32(16, 23)