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Searched refs:PPC_BIT (Results 1 – 25 of 32) sorted by relevance

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/qemu/include/hw/pci-host/
H A Dpnv_phb4_regs.h75 #define PEC_NEST_STK_BAR_EN_MMIO0 PPC_BIT(0)
76 #define PEC_NEST_STK_BAR_EN_MMIO1 PPC_BIT(1)
77 #define PEC_NEST_STK_BAR_EN_PHB PPC_BIT(2)
78 #define PEC_NEST_STK_BAR_EN_INT PPC_BIT(3)
111 #define PHB_SCOM_HV_IND_ADDR_VALID PPC_BIT(0)
112 #define PHB_SCOM_HV_IND_ADDR_4B PPC_BIT(1)
113 #define PHB_SCOM_HV_IND_ADDR_AUTOINC PPC_BIT(2)
140 #define PHB_DMA_CHAN_ANY_ERR PPC_BIT(27)
141 #define PHB_DMA_CHAN_ANY_ERR1 PPC_BIT(28)
142 #define PHB_DMA_CHAN_ANY_FREEZE PPC_BIT(29)
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H A Dpnv_phb3_regs.h31 #define PBCQ_NEST_BAR_EN_MMIO0 PPC_BIT(0)
32 #define PBCQ_NEST_BAR_EN_MMIO1 PPC_BIT(1)
33 #define PBCQ_NEST_BAR_EN_PHB PPC_BIT(2)
34 #define PBCQ_NEST_BAR_EN_IRSN_RX PPC_BIT(3)
35 #define PBCQ_NEST_BAR_EN_IRSN_TX PPC_BIT(4)
55 #define PHB_DMA_CHAN_ANY_ERR PPC_BIT(27)
56 #define PHB_DMA_CHAN_ANY_ERR1 PPC_BIT(28)
57 #define PHB_DMA_CHAN_ANY_FREEZE PPC_BIT(29)
59 #define PHB_CPU_LS_ANY_ERR PPC_BIT(27)
60 #define PHB_CPU_LS_ANY_ERR1 PPC_BIT(28)
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/qemu/include/hw/i2c/
H A Dpnv_i2c_regs.h18 #define I2C_CMD_WITH_START PPC_BIT(0)
19 #define I2C_CMD_WITH_ADDR PPC_BIT(1)
20 #define I2C_CMD_READ_CONT PPC_BIT(2)
21 #define I2C_CMD_WITH_STOP PPC_BIT(3)
26 #define I2C_CMD_READ_NOT_WRITE PPC_BIT(15)
34 #define I2C_MODE_ENHANCED PPC_BIT(28)
35 #define I2C_MODE_DIAGNOSTIC PPC_BIT(29)
36 #define I2C_MODE_PACING_ALLOW PPC_BIT(30)
37 #define I2C_MODE_WRAP PPC_BIT(31)
62 #define I2C_INTR_INVALID_CMD PPC_BIT(16)
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/qemu/hw/intc/
H A Dpnv_xive_regs.h25 #define CQ_IC_BAR_VALID PPC_BIT(0)
26 #define CQ_IC_BAR_64K PPC_BIT(1)
29 #define CQ_TM_BAR_VALID PPC_BIT(0)
30 #define CQ_TM_BAR_64K PPC_BIT(1)
32 #define CQ_PC_BAR_VALID PPC_BIT(0)
36 #define CQ_VC_BAR_VALID PPC_BIT(0)
40 #define CQ_TAR_TBL_AUTOINC PPC_BIT(0)
42 #define CQ_TAR_TSEL_BLK PPC_BIT(12)
43 #define CQ_TAR_TSEL_MIG PPC_BIT(13)
44 #define CQ_TAR_TSEL_VDT PPC_BIT(14)
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H A Dpnv_xive2_regs.h33 #define CQ_XIVE_CAP_VP_SAVE_RESTORE PPC_BIT(38)
35 #define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56)
36 #define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57)
37 #define CQ_XIVE_CAP_EXPLOITATION_MODE PPC_BIT(58)
38 #define CQ_XIVE_CAP_STORE_EOI PPC_BIT(59)
61 #define CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE PPC_BIT(16)
64 #define CQ_XIVE_CFG_GEN1_TIMA_OS PPC_BIT(24)
65 #define CQ_XIVE_CFG_GEN1_TIMA_HYP PPC_BIT(25)
66 #define CQ_XIVE_CFG_GEN1_TIMA_HYP_BLK0 PPC_BIT(26) /* 0 if bit[25]=0 */
67 #define CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS PPC_BIT(27) /* 0 if bit[25]=0 */
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H A Dspapr_xive.c927 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */
928 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */
929 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management
931 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */
1042 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62)
1043 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63)
1315 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63)
1486 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63)
1676 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63)
/qemu/include/hw/ssi/
H A Dpnv_spi_regs.h17 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) macro
19 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
35 #define SPI_CTR_CFG_N1_CTRL_B1 PPC_BIT(49)
36 #define SPI_CTR_CFG_N1_CTRL_B2 PPC_BIT(50)
37 #define SPI_CTR_CFG_N1_CTRL_B3 PPC_BIT(51)
38 #define SPI_CTR_CFG_N2_CTRL_B0 PPC_BIT(52)
39 #define SPI_CTR_CFG_N2_CTRL_B1 PPC_BIT(53)
40 #define SPI_CTR_CFG_N2_CTRL_B2 PPC_BIT(54)
41 #define SPI_CTR_CFG_N2_CTRL_B3 PPC_BIT(55)
50 #define SPI_CLK_CFG_ECC_EN PPC_BIT(28)
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/qemu/target/ppc/
H A Dcpu.h44 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) macro
48 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
529 #define MMCR0_FC PPC_BIT(32) /* Freeze Counters */
530 #define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Occurred */
531 #define MMCR0_PMAE PPC_BIT(37) /* Perf Monitor Alert Enable */
532 #define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */
533 #define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */
534 #define MMCR0_PMCC0 PPC_BIT(44) /* PMC Control bit 0 */
535 #define MMCR0_PMCC1 PPC_BIT(45) /* PMC Control bit 1 */
537 #define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */
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H A Dtcg-excp_helper.c262 env->spr[SPR_DSISR] = PPC_BIT(57); in ppc_cpu_do_transaction_failed()
263 env->error_code = PPC_BIT(42); in ppc_cpu_do_transaction_failed()
271 env->error_code = PPC_BIT(36) | PPC_BIT(43) | PPC_BIT(45); in ppc_cpu_do_transaction_failed()
272 env->error_code |= PPC_BIT(42); in ppc_cpu_do_transaction_failed()
279 env->error_code = PPC_BIT(36) | PPC_BIT(44) | PPC_BIT(45); in ppc_cpu_do_transaction_failed()
304 env->spr[SPR_DSISR] = PPC_BIT(41); in ppc_cpu_debug_excp_handler()
311 PPC_BIT(33) | PPC_BIT(43)); in ppc_cpu_debug_excp_handler()
847 error_code = PPC_BIT(33); in helper_book3s_trace()
H A Dmisc_helper.c352 return PPC_BIT(63); in helper_load_sprd()
402 val |= PPC_BIT(63); /* verion 0x1 (POWER9/10) */ in helper_load_pmsr()
425 val |= PPC_BIT(63); in helper_store_pmcr()
H A Dexcp_helper.c1205 if (!(env->error_code & PPC_BIT(42))) { in is_prefix_insn_excp()
1294 msr |= PPC_BIT(34); in powerpc_excp_books()
/qemu/hw/ppc/
H A Dpnv_psi.c593 #define PSIHB9_IRQ_METHOD PPC_BIT(0)
594 #define PSIHB9_IRQ_RESET PPC_BIT(1)
597 #define PSIHB9_ESB_CI_VALID PPC_BIT(63)
600 #define PSIHB9_ESB_NOTIF_VALID PPC_BIT(63)
605 #define PSIHB9_IRQ_LEVEL_PSI PPC_BIT(0)
606 #define PSIHB9_IRQ_LEVEL_OCC PPC_BIT(1)
607 #define PSIHB9_IRQ_LEVEL_FSI PPC_BIT(2)
608 #define PSIHB9_IRQ_LEVEL_LPCHC PPC_BIT(3)
609 #define PSIHB9_IRQ_LEVEL_LOCAL_ERR PPC_BIT(4)
610 #define PSIHB9_IRQ_LEVEL_GLOBAL_ERR PPC_BIT(5)
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H A Dpnv_chiptod.c119 val |= PPC_BIT(12); /* Primary config master path select */ in pnv_chiptod_xscom_read()
121 val |= PPC_BIT(20); /* Is running */ in pnv_chiptod_xscom_read()
123 val |= PPC_BIT(21); /* Is using primary config */ in pnv_chiptod_xscom_read()
124 val |= PPC_BIT(26); /* Is using master path select */ in pnv_chiptod_xscom_read()
127 val |= PPC_BIT(23); /* Is active master */ in pnv_chiptod_xscom_read()
129 val |= PPC_BIT(24); /* Is backup master */ in pnv_chiptod_xscom_read()
131 val |= PPC_BIT(25); /* Is slave (should backup master set this?) */ in pnv_chiptod_xscom_read()
145 val |= PPC_BIT(4); in pnv_chiptod_xscom_read()
237 if (val & PPC_BIT(35)) { /* SCOM addressing */ in chiptod_power9_tx_ttype_target()
262 if (val & PPC_BIT(35)) { /* SCOM addressing */ in chiptod_power10_tx_ttype_target()
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H A Dpnv_core.c63 env->spr[SPR_PVR] &= ~PPC_BIT(51); in pnv_core_cpu_reset()
208 val |= PPC_BIT(56 + i); in pnv_core_power10_xscom_read()
212 val |= PPC_BIT(62); in pnv_core_power10_xscom_read()
222 val |= PPC_BIT(0 + 8 * i) | PPC_BIT(1 + 8 * i); in pnv_core_power10_xscom_read()
249 if (val & PPC_BIT(7 + 8 * i)) { /* stop */ in pnv_core_power10_xscom_write()
250 val &= ~PPC_BIT(7 + 8 * i); in pnv_core_power10_xscom_write()
255 if (val & PPC_BIT(6 + 8 * i)) { /* start */ in pnv_core_power10_xscom_write()
256 val &= ~PPC_BIT(6 + 8 * i); in pnv_core_power10_xscom_write()
261 if (val & PPC_BIT(4 + 8 * i)) { /* sreset */ in pnv_core_power10_xscom_write()
262 val &= ~PPC_BIT(4 + 8 * i); in pnv_core_power10_xscom_write()
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H A Dpnv_sbe.c61 #define HOST_SBE_MSG_WAITING PPC_BIT(0)
67 #define SBE_HOST_RESPONSE_WAITING PPC_BIT(0)
68 #define SBE_HOST_MSG_READ PPC_BIT(1)
69 #define SBE_HOST_STOP15_EXIT PPC_BIT(2)
70 #define SBE_HOST_RESET PPC_BIT(3)
71 #define SBE_HOST_PASSTHROUGH PPC_BIT(4)
72 #define SBE_HOST_TIMER_EXPIRY PPC_BIT(14)
80 #define SBE_CONTROL_REG_S0 PPC_BIT(14)
81 #define SBE_CONTROL_REG_S1 PPC_BIT(15)
H A Dpnv_adu.c60 val = PPC_BIT(0); /* ack / done */ in pnv_adu_xscom_read()
75 return !!(adu->lpc_cmd_reg & PPC_BIT(0)); in lpc_cmd_read()
H A Dpnv_lpc.c255 #define ECCB_CTL_READ PPC_BIT(15)
260 #define ECCB_STAT_OP_DONE PPC_BIT(52)
261 #define ECCB_STAT_OP_ERR PPC_BIT(52)
H A Dpnv_occ.c37 #define OCCMISC_PSI_IRQ PPC_BIT(0)
38 #define OCCMISC_IRQ_SHMEM PPC_BIT(3)
H A Dspapr_nvdimm.c41 #define PAPR_PMEM_UNARMED PPC_BIT(0)
H A Dspapr_events.c322 #define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42))
/qemu/include/hw/ppc/
H A Dspapr.h433 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0)
434 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1)
435 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2)
436 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3)
437 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4)
438 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5)
439 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6)
440 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7)
441 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9)
443 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0)
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H A Dxive_regs.h38 #define XIVE_TRIGGER_END PPC_BIT(0)
39 #define XIVE_TRIGGER_PQ PPC_BIT(1)
186 #define EAS_VALID PPC_BIT(0)
189 #define EAS_MASKED PPC_BIT(32) /* Masked */
H A Dxive2_regs.h42 #define EAS2_VALID PPC_BIT(0)
45 #define EAS2_MASKED PPC_BIT(32) /* Masked */
/qemu/tests/qtest/
H A Dpnv-xive2-common.h12 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) macro
15 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
H A Dpnv-host-i2c-test.c15 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) macro
18 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))

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