Lines Matching refs:PPC_BIT
44 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) macro
48 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
529 #define MMCR0_FC PPC_BIT(32) /* Freeze Counters */
530 #define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Occurred */
531 #define MMCR0_PMAE PPC_BIT(37) /* Perf Monitor Alert Enable */
532 #define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */
533 #define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */
534 #define MMCR0_PMCC0 PPC_BIT(44) /* PMC Control bit 0 */
535 #define MMCR0_PMCC1 PPC_BIT(45) /* PMC Control bit 1 */
537 #define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */
538 #define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */
539 #define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */
540 #define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */
541 #define MMCR0_FCP PPC_BIT(34) /* Freeze Counters/BHRB if PR=1 */
542 #define MMCR0_FCPC PPC_BIT(51) /* Condition for FCP bit */
547 #define MMCR2_FC1P0 PPC_BIT(1) /* MMCR2 FCnP0 for PMC1 */
548 #define MMCR2_FC2P0 PPC_BIT(10) /* MMCR2 FCnP0 for PMC2 */
549 #define MMCR2_FC3P0 PPC_BIT(19) /* MMCR2 FCnP0 for PMC3 */
550 #define MMCR2_FC4P0 PPC_BIT(28) /* MMCR2 FCnP0 for PMC4 */
551 #define MMCR2_FC5P0 PPC_BIT(37) /* MMCR2 FCnP0 for PMC5 */
552 #define MMCR2_FC6P0 PPC_BIT(46) /* MMCR2 FCnP0 for PMC6 */
556 #define MMCRA_BHRBRD PPC_BIT(26) /* BHRB Recording Disable */
572 #define CTRL_RUN PPC_BIT(63)
576 #define BESCR_GE PPC_BIT(0)
578 #define BESCR_EE PPC_BIT(30)
580 #define BESCR_PME PPC_BIT(31)
582 #define BESCR_EEO PPC_BIT(62)
584 #define BESCR_PMEO PPC_BIT(63)
588 #define LPCR_VPM0 PPC_BIT(0)
589 #define LPCR_VPM1 PPC_BIT(1)
590 #define LPCR_ISL PPC_BIT(2)
591 #define LPCR_KBV PPC_BIT(3)
599 #define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */
602 #define LPCR_HAIL PPC_BIT(37) /* ISA v3.1 HV AIL=3 equivalent */
603 #define LPCR_ILE PPC_BIT(38)
606 #define LPCR_UPRT PPC_BIT(41) /* Use Process Table */
607 #define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */
608 #define LPCR_HR PPC_BIT(43) /* Host Radix */
609 #define LPCR_ONL PPC_BIT(45)
610 #define LPCR_LD PPC_BIT(46) /* Large Decrementer */
611 #define LPCR_P7_PECE0 PPC_BIT(49)
612 #define LPCR_P7_PECE1 PPC_BIT(50)
613 #define LPCR_P7_PECE2 PPC_BIT(51)
614 #define LPCR_P8_PECE0 PPC_BIT(47)
615 #define LPCR_P8_PECE1 PPC_BIT(48)
616 #define LPCR_P8_PECE2 PPC_BIT(49)
617 #define LPCR_P8_PECE3 PPC_BIT(50)
618 #define LPCR_P8_PECE4 PPC_BIT(51)
622 #define LPCR_PDEE PPC_BIT(47) /* Privileged Doorbell Exit EN */
623 #define LPCR_HDEE PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
624 #define LPCR_EEE PPC_BIT(49) /* External Exit Enable */
625 #define LPCR_DEE PPC_BIT(50) /* Decrementer Exit Enable */
626 #define LPCR_OEE PPC_BIT(51) /* Other Exit Enable */
627 #define LPCR_MER PPC_BIT(52)
628 #define LPCR_GTSE PPC_BIT(53) /* Guest Translation Shootdown */
629 #define LPCR_TC PPC_BIT(54)
630 #define LPCR_HEIC PPC_BIT(59) /* HV Extern Interrupt Control */
631 #define LPCR_LPES0 PPC_BIT(60)
632 #define LPCR_LPES1 PPC_BIT(61)
633 #define LPCR_RMI PPC_BIT(62)
634 #define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */
635 #define LPCR_HDICE PPC_BIT(63)
638 #define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */
639 #define PSSCR_EC PPC_BIT(43) /* Exit Criterion */
716 #define ESR_PIL PPC_BIT(36) /* Illegal Instruction */
717 #define ESR_PPR PPC_BIT(37) /* Privileged Instruction */
718 #define ESR_PTR PPC_BIT(38) /* Trap */
719 #define ESR_FP PPC_BIT(39) /* Floating-Point Operation */
720 #define ESR_ST PPC_BIT(40) /* Store Operation */
721 #define ESR_AP PPC_BIT(44) /* Auxiliary Processor Operation */
722 #define ESR_PUO PPC_BIT(45) /* Unimplemented Operation */
723 #define ESR_BO PPC_BIT(46) /* Byte Ordering */
724 #define ESR_PIE PPC_BIT(47) /* Imprecise exception */
725 #define ESR_DATA PPC_BIT(53) /* Data Access (Embedded page table) */
726 #define ESR_TLBI PPC_BIT(54) /* TLB Ineligible (Embedded page table) */
727 #define ESR_PT PPC_BIT(55) /* Page Table (Embedded page table) */
728 #define ESR_SPV PPC_BIT(56) /* SPE/VMX operation */
729 #define ESR_EPID PPC_BIT(57) /* External Process ID operation */
730 #define ESR_VLEMI PPC_BIT(58) /* VLE operation */
731 #define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */
919 #define FPSCR_MTFS_MASK (~(MAKE_64BIT_MASK(36, 28) | PPC_BIT(28) | \
920 FP_FEX | FP_VX | PPC_BIT(52)))
2331 #define HID0_HILE PPC_BIT(19) /* POWER8 */
2332 #define HID0_POWER9_HILE PPC_BIT(4)
2333 #define HID0_ENABLE_ATTN PPC_BIT(31) /* POWER8 */
2334 #define HID0_POWER9_ENABLE_ATTN PPC_BIT(3)
2686 PCR_COMPAT_2_05 = PPC_BIT(62),
2687 PCR_COMPAT_2_06 = PPC_BIT(61),
2688 PCR_COMPAT_2_07 = PPC_BIT(60),
2689 PCR_COMPAT_3_00 = PPC_BIT(59),
2690 PCR_COMPAT_3_10 = PPC_BIT(58),
2691 PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2692 PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2693 PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */
2698 HMER_MALFUNCTION_ALERT = PPC_BIT(0),
2699 HMER_PROC_RECV_DONE = PPC_BIT(2),
2700 HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2701 HMER_TFAC_ERROR = PPC_BIT(4),
2702 HMER_TFMR_PARITY_ERROR = PPC_BIT(5),
2703 HMER_XSCOM_FAIL = PPC_BIT(8),
2704 HMER_XSCOM_DONE = PPC_BIT(9),
2705 HMER_PROC_RECV_AGAIN = PPC_BIT(11),
2706 HMER_WARN_RISE = PPC_BIT(14),
2707 HMER_WARN_FALL = PPC_BIT(15),
2708 HMER_SCOM_FIR_HMI = PPC_BIT(16),
2709 HMER_TRIG_FIR_HMI = PPC_BIT(17),
2710 HMER_HYP_RESOURCE_ERR = PPC_BIT(20),
2717 TFMR_MASK_HMI = PPC_BIT(10),
2718 TFMR_TB_ECLIPZ = PPC_BIT(14),
2719 TFMR_LOAD_TOD_MOD = PPC_BIT(16),
2720 TFMR_MOVE_CHIP_TOD_TO_TB = PPC_BIT(18),
2721 TFMR_CLEAR_TB_ERRORS = PPC_BIT(24),
2725 TFMR_TB_ENABLED = PPC_BIT(40),
2726 TFMR_TB_VALID = PPC_BIT(41),
2727 TFMR_TB_SYNC_OCCURED = PPC_BIT(42),
2728 TFMR_FIRMWARE_CONTROL_ERROR = PPC_BIT(46),