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/qemu/target/hexagon/
H A Dattribs_def.h.inc42 DEF_ATTRIB(MEMSIZE_0B, "Memory width is 0 byte", "", "")
43 DEF_ATTRIB(MEMSIZE_1B, "Memory width is 1 byte", "", "")
44 DEF_ATTRIB(MEMSIZE_2B, "Memory width is 2 bytes", "", "")
45 DEF_ATTRIB(MEMSIZE_4B, "Memory width is 4 bytes", "", "")
46 DEF_ATTRIB(MEMSIZE_8B, "Memory width is 8 bytes", "", "")
49 DEF_ATTRIB(REGWRSIZE_1B, "Memory width is 1 byte", "", "")
50 DEF_ATTRIB(REGWRSIZE_2B, "Memory width is 2 bytes", "", "")
51 DEF_ATTRIB(REGWRSIZE_4B, "Memory width is 4 bytes", "", "")
52 DEF_ATTRIB(REGWRSIZE_8B, "Memory width is 8 bytes", "", "")
53 DEF_ATTRIB(MEMLIKE, "Memory-like instruction", "", "")
[all …]
/qemu/docs/specs/
H A Dacpi_mem_hotplug.rst7 Memory hot-plug interface (IO port 0xa00-0xa17, 1-4 byte access)
22 Memory device proximity domain
24 Memory device status fields
48 Memory device slot selector, selects active memory device.
58 Memory device control fields
87 Memory hot remove process diagram
H A Dacpi_hw_reduced_hotplug.rst64 0: Memory hotplug event
H A Dstandard-vga.rst60 Memory regions used
H A Dppc-xive.rst85 Memory | +-------+
91 Memory | ESB | | EAT | | ENDT | | NVTT |
/qemu/target/hexagon/imported/
H A Dsystem.idef38 Q6INSN(Y2_isync,"isync",ATTRIBS(),"Memory Synchronization",{fISYNC();})
39 Q6INSN(Y2_barrier,"barrier",ATTRIBS(A_RESTRICT_SLOT0ONLY),"Memory Barrier",{fBARRIER();})
40 Q6INSN(Y2_syncht,"syncht",ATTRIBS(A_RESTRICT_SLOT0ONLY),"Memory Synchronization",{fSYNCH();})
H A Dldst.idef298 STD_MEMOP_AMODES(add_memop, "+=Rt32", "Add Register to Memory Word", tmp += RtV)
299 STD_MEMOP_AMODES(sub_memop, "-=Rt32", "Sub Register from Memory Word", tmp -= RtV)
300 STD_MEMOP_AMODES(and_memop, "&=Rt32", "Logical AND Register to Memory Word", tmp &= RtV)
301 STD_MEMOP_AMODES(or_memop, "|=Rt32", "Logical OR Register to Memory Word", tmp |= RtV)
304 STD_MEMOP_AMODES(iadd_memop, "+=#U5", "Add Immediate to Memory Word", tmp += UiV)
305 STD_MEMOP_AMODES(isub_memop, "-=#U5", "Sub Immediate to Memory Word", tmp -= UiV)
/qemu/docs/system/devices/
H A Dcxl.rst34 * Memory operations
58 **Type 3 Memory devices:** These devices act as a means of attaching
81 CXL Fixed Memory Windows (CFMW)
106 * Configuration of HDM Decoders to route CXL Memory accesses with
142 CXL Memory Devices - Type 3
150 CXL Memory Interleave
165 | | CFMW 0 | | CXL Fixed Memory Window 1 | | CFMW 2 | |
208 (1) **3 CXL Fixed Memory Windows (CFMW)** corresponding to different
250 | | CFMW 0 | | CXL Fixed Memory Window 1 | | CFMW 2 | |
303 A very simple setup with just one directly attached CXL Type 3 Persistent Memory device::
[all …]
H A Dnvme.rst11 * Configuration of `Optional Features`_ such as `Controller Memory Buffer`_,
157 Controller Memory Buffer
160 ``nvme`` device parameters related to the Controller Memory Buffer support:
163 This adds a Controller Memory Buffer of the given size at offset zero in BAR
167 By default, the device uses the "v1.4 scheme" for the Controller Memory
H A Divshmem.rst1 Inter-VM Shared Memory device
H A Divshmem-flat.rst1 Inter-VM Shared Memory Flat Device
/qemu/qapi/
H A Dcxl.json49 # @descriptor: Memory Event Descriptor with additional memory event
51 # Record, Memory Event Descriptor for bit definitions.
54 # General Media Event Record, Memory Event Type for possible
100 # @descriptor: Memory Event Descriptor with additional memory event
101 # information. See CXL r3.0 Table 8-44 DRAM Event Record, Memory
105 # DRAM Event Record, Memory Event Type for possible values.
146 # Inject an event record for a Memory Module Event (CXL r3.0
157 # @type: Device Event Type. See CXL r3.0 Table 8-45 Memory Module
/qemu/docs/system/arm/
H A Demulation.rst95 - FEAT_MTE (Memory Tagging Extension)
96 - FEAT_MTE2 (Memory Tagging Extension)
98 - FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults)
188 - MPU (Memory Protection Unit Extension)
H A Daspeed.rst52 * Static Memory Controller (SMC or FMC) - Only SPI Flash support
53 * SPI Memory Controller
269 * Static Memory Controller (SMC or FMC) - Only SPI Flash support
270 * SPI Memory Controller
441 * Static Memory Controller (SMC or FMC) - Only SPI Flash support
442 * SPI Memory Controller
H A Dxlnx-zynq.rst27 - DDR Memory
/qemu/docs/
H A Digd-assign.txt13 * Data Stolen Memory (DSM) region used as VRAM at early stage (BIOS/UEFI)
133 Memory (BDSM) in guest address space. IGD passthrough support imposes two
209 Memory View
227 The memory region store GTT is called GTT Stolen Memory (GSM) it is located
228 right below the Data Stolen Memory (DSM). Accessing this region directly is
232 The Data Stolen Memory is reserved by firmware, and acts as the VRAM in pre-OS
/qemu/docs/devel/migration/
H A Dqatzip-compression.rst120 QAT Memory Requirements
127 Because memory usage depends on QAT configuration, please refer to `QAT Memory
H A Dqpl-compression.rst8 The ``QPL`` compression relies on Intel In-Memory Analytics Accelerator(``IAA``)
9 and Shared Virtual Memory(``SVM``) technology, they are new features supported
176 Shared Virtual Memory(SVM) Introduction
/qemu/docs/devel/
H A Dmulti-thread-tcg.rst171 Memory maps and TLBs
183 - Memory regions (dividing up access to PIO, MMIO and RAM)
250 Memory Consistency
258 Memory Barriers
314 Memory Control and Maintenance
H A Dtcg-plugins.rst117 Memory Accesses
120 Memory callbacks are called after a successful load or store.
/qemu/tests/tcg/hexagon/
H A Dmem_noshuf.c196 } Memory; typedef
200 Memory n; in main()
/qemu/target/arm/tcg/
H A Dsme.decode41 ### SME Memory
/qemu/docs/system/loongarch/
H A Dvirt.rst22 * Memory device
/qemu/include/exec/
H A Dmemory_ldst_cached.h.inc2 * Memory access templates for MemoryRegionCache
/qemu/tests/functional/acpi-bits/bits-tests/
H A Dsmbios.py2243 8: 'Memory Module',
246 0xB: 'Processor/Memory Module',
598 0b10: 'Varies with Memory Address',
792 0x0B: 'Proprietary Memory Card Slot',
997 0x03: 'Memory-mapped physical 32-bit address',
1045 0x07: 'POST Memory Resize',
1276 0x04: 'Memory partition level'
1589 0b01000: 'Memory Module',
1693 0b01000: 'Memory Module',
1752 0b01000: 'Memory Module',
[all …]

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