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Searched refs:MES (Results 1 – 5 of 5) sorted by relevance

/linux/Documentation/gpu/amdgpu/gc/
H A Dmes.rst4 MicroEngine Scheduler (MES)
18 Scheduler (MES). Whenever the driver is initialized, it creates one MQD per
19 hardware queue, and then the MQDs are handed to the MES firmware for mapping
34 In terms of User Queues, MES can dynamically map them to the HQD. If there are
35 more MQDs than HQDs, the MES firmware will preempt other user queues to make
36 sure each queues get a time slice; in other words, MES is a microcontroller
H A Dindex.rst40 MES (MicroEngine Scheduler)
42 :ref:`MicroEngine Scheduler (MES) <amdgpu-mes>`.
/linux/Documentation/gpu/amdgpu/
H A Ddriver-core.rst112 3. Other hardware requests the change (e.g., MES).
120 deactivating a given Queue. The scheduling firmware (e.g., MES) is responsible
143 map/unmap additional queues, etc. This is replaced by MES on
H A Damdgpu-glossary.rst134 MES
/linux/drivers/infiniband/hw/hfi1/
H A Dchip.c343 #define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK macro
345 /* 0*/ FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)),
346 /* 1*/ FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)),
347 /* 2*/ FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)),
348 /* 3*/ FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED)),
349 /* 4*/ FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH)),
350 /* 5*/ FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED)),
351 /* 6*/ FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY)),
352 /* 7*/ FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR)),
353 /* 8*/ FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRIT
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