1.. _amdgpu-gc:
2
3========================================
4 drm/amdgpu - Graphics and Compute (GC)
5========================================
6
7The relationship between the CPU and GPU can be described as the
8producer-consumer problem, where the CPU fills out a buffer with operations
9(producer) to be executed by the GPU (consumer). The requested operations in
10the buffer are called Command Packets, which can be summarized as a compressed
11way of transmitting command information to the graphics controller.
12
13The component that acts as the front end between the CPU and the GPU is called
14the Command Processor (CP). This component is responsible for providing greater
15flexibility to the GC since CP makes it possible to program various aspects of
16the GPU pipeline. CP also coordinates the communication between the CPU and GPU
17via a mechanism named **Ring Buffers**, where the CPU appends information to
18the buffer while the GPU removes operations. It is relevant to highlight that a
19CPU can add a pointer to the Ring Buffer that points to another region of
20memory outside the Ring Buffer, and CP can handle it; this mechanism is called
21**Indirect Buffer (IB)**. CP receives and parses the Command Streams (CS), and
22writes the operations to the correct hardware blocks.
23
24Graphics (GFX) and Compute Microcontrollers
25-------------------------------------------
26
27GC is a large block, and as a result, it has multiple firmware associated with
28it. Some of them are:
29
30CP (Command Processor)
31    The name for the hardware block that encompasses the front end of the
32    GFX/Compute pipeline. Consists mainly of a bunch of microcontrollers
33    (PFP, ME, CE, MEC). The firmware that runs on these microcontrollers
34    provides the driver interface to interact with the GFX/Compute engine.
35
36    MEC (MicroEngine Compute)
37        This is the microcontroller that controls the compute queues on the
38        GFX/compute engine.
39
40    MES (MicroEngine Scheduler)
41        This is the engine for managing queues. For more details check
42        :ref:`MicroEngine Scheduler (MES) <amdgpu-mes>`.
43
44RLC (RunList Controller)
45    This is another microcontroller in the GFX/Compute engine. It handles
46    power management related functionality within the GFX/Compute engine.
47    The name is a vestige of old hardware where it was originally added
48    and doesn't really have much relation to what the engine does now.
49
50.. toctree::
51
52   mes.rst
53