1.. _amdgpu-mes:
2
3=============================
4 MicroEngine Scheduler (MES)
5=============================
6
7.. note::
8   Queue and ring buffer are used as a synonymous.
9
10.. note::
11   This section assumes that you are familiar with the concept of Pipes, Queues, and GC.
12   If not, check :ref:`GFX, Compute, and SDMA Overall Behavior<pipes-and-queues-description>`
13   and :ref:`drm/amdgpu - Graphics and Compute (GC) <amdgpu-gc>`.
14
15Every GFX has a pipe component with one or more hardware queues. Pipes can
16switch between queues depending on certain conditions, and one of the
17components that can request a queue switch to a pipe is the MicroEngine
18Scheduler (MES). Whenever the driver is initialized, it creates one MQD per
19hardware queue, and then the MQDs are handed to the MES firmware for mapping
20to:
21
221. Kernel Queues (legacy): This queue is statically mapped to HQDs and never
23   preempted. Even though this is a legacy feature, it is the current default, and
24   most existing hardware supports it. When an application submits work to the
25   kernel driver, it submits all of the application command buffers to the kernel
26   queues. The CS IOCTL takes the command buffer from the applications and
27   schedules them on the kernel queue.
28
292. User Queues: These queues are dynamically mapped to the HQDs. Regarding the
30   utilization of User Queues, the userspace application will create its user
31   queues and submit work directly to its user queues with no need to IOCTL for
32   each submission and no need to share a single kernel queue.
33
34In terms of User Queues, MES can dynamically map them to the HQD. If there are
35more MQDs than HQDs, the MES firmware will preempt other user queues to make
36sure each queues get a time slice; in other words, MES is a microcontroller
37that handles the mapping and unmapping of MQDs into HQDs, as well as the
38priorities and oversubscription of MQDs.
39