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Searched refs:gpu_write (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/msm/adreno/
H A Da3xx_gpu.c123 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
124 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010); in a3xx_hw_init()
125 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
126 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
127 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303); in a3xx_hw_init()
128 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
129 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010); in a3xx_hw_init()
131 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff); in a3xx_hw_init()
133 gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030); in a3xx_hw_init()
135 gpu_write(gp in a3xx_hw_init()
[all...]
H A Da4xx_gpu.c81 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
83 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
85 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
87 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
89 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_SP(i), 0x22222222); in a4xx_enable_hwcg()
91 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_SP(i), 0x00222222); in a4xx_enable_hwcg()
93 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_SP(i), 0x00000104); in a4xx_enable_hwcg()
95 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_SP(i), 0x00000081); in a4xx_enable_hwcg()
96 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_UCHE, 0x22222222); in a4xx_enable_hwcg()
97 gpu_write(gp in a4xx_enable_hwcg()
[all...]
H A Da5xx_power.c130 gpu_write(gpu, a5xx_sequence_regs[i].reg, in a530_lm_setup()
134 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, 0x60007); in a530_lm_setup()
135 gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01); in a530_lm_setup()
136 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01); in a530_lm_setup()
139 gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0); in a530_lm_setup()
141 gpu_write(gpu, REG_A5XX_GPMU_BASE_LEAKAGE, a5xx_gpu->lm_leakage); in a530_lm_setup()
144 gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000); in a530_lm_setup()
146 gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF); in a530_lm_setup()
147 gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x00201FF1); in a530_lm_setup()
150 gpu_write(gp in a530_lm_setup()
[all...]
H A Da6xx_gpu.c89 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); in a6xx_flush()
544 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); in a6xx_set_hwcg()
545 gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); in a6xx_set_hwcg()
548 gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1); in a6xx_set_hwcg()
556 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0); in a6xx_set_hwcg()
573 gpu_write(gpu, reg->offset, state ? reg->value : 0); in a6xx_set_hwcg()
579 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); in a6xx_set_hwcg()
593 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, in a6xx_set_cp_protect()
601 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), protect->regs[i]); in a6xx_set_cp_protect()
604 gpu_write(gp in a6xx_set_cp_protect()
[all...]
H A Da6xx_gpu_state.c163 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); in a6xx_crashdumper_run()
168 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0); in a6xx_crashdumper_run()
180 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_A, reg); in debugbus_read()
181 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_B, reg); in debugbus_read()
182 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_C, reg); in debugbus_read()
183 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_D, reg); in debugbus_read()
227 gpu_write(gpu, ctrl0, reg); in vbif_debugbus_read()
230 gpu_write(gpu, ctrl1, i); in vbif_debugbus_read()
264 gpu_write(gpu, REG_A6XX_VBIF_CLKON, in a6xx_get_vbif_debugbus_block()
268 gpu_write(gp in a6xx_get_vbif_debugbus_block()
[all...]
H A Da5xx_debugfs.c21 gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, i); in pfp_print()
34 gpu_write(gpu, REG_A5XX_CP_ME_STAT_ADDR, i); in me_print()
45 gpu_write(gpu, REG_A5XX_CP_MEQ_DBG_ADDR, 0); in meq_print()
58 gpu_write(gpu, REG_A5XX_CP_ROQ_DBG_ADDR, 0); in roq_print()
H A Da2xx_gpummu.c56 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_map()
71 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_unmap()
H A Da6xx_preempt.c54 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); in update_wptr()
213 gpu_write(gpu, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0x1); in a6xx_preempt_hw_init()
331 gpu_write(gpu, REG_A6XX_CP_CONTEXT_SWITCH_CNTL, cntl); in a6xx_preempt_trigger()
H A Da5xx_preempt.c52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
168 gpu_write(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL, 1); in a5xx_preempt_trigger()
H A Dadreno_gpu.c742 gpu_write(gpu, reg, wptr); in adreno_flush()
/linux/drivers/gpu/drm/panfrost/
H A Dpanfrost_perfcnt.c45 gpu_write(pfdev, GPU_CMD, GPU_CMD_CLEAN_CACHES); in panfrost_perfcnt_sample_done()
55 gpu_write(pfdev, GPU_PERFCNT_BASE_LO, lower_32_bits(gpuva)); in panfrost_perfcnt_dump_locked()
56 gpu_write(pfdev, GPU_PERFCNT_BASE_HI, upper_32_bits(gpuva)); in panfrost_perfcnt_dump_locked()
57 gpu_write(pfdev, GPU_INT_CLEAR, in panfrost_perfcnt_dump_locked()
60 gpu_write(pfdev, GPU_CMD, GPU_CMD_PERFCNT_SAMPLE); in panfrost_perfcnt_dump_locked()
121 gpu_write(pfdev, GPU_INT_CLEAR, in panfrost_perfcnt_enable_locked()
124 gpu_write(pfdev, GPU_CMD, GPU_CMD_PERFCNT_CLEAR); in panfrost_perfcnt_enable_locked()
125 gpu_write(pfdev, GPU_CMD, GPU_CMD_CLEAN_INV_CACHES); in panfrost_perfcnt_enable_locked()
146 gpu_write(pfdev, GPU_PRFCNT_JM_EN, 0xffffffff); in panfrost_perfcnt_enable_locked()
147 gpu_write(pfde in panfrost_perfcnt_enable_locked()
[all...]
H A Dpanfrost_gpu.c46 gpu_write(pfdev, GPU_INT_MASK, 0); in panfrost_gpu_irq_handler()
55 gpu_write(pfdev, GPU_INT_CLEAR, state); in panfrost_gpu_irq_handler()
65 gpu_write(pfdev, GPU_INT_MASK, 0); in panfrost_gpu_soft_reset()
66 gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED); in panfrost_gpu_soft_reset()
70 gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); in panfrost_gpu_soft_reset()
77 gpu_write(pfdev, GPU_CMD, GPU_CMD_HARD_RESET); in panfrost_gpu_soft_reset()
86 gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL); in panfrost_gpu_soft_reset()
89 gpu_write(pfdev, GPU_INT_MASK, in panfrost_gpu_soft_reset()
111 gpu_write(pfdev, GPU_PWR_KEY, GPU_PWR_KEY_UNLOCK); in panfrost_gpu_amlogic_quirk()
112 gpu_write(pfde in panfrost_gpu_amlogic_quirk()
[all...]
H A Dpanfrost_regs.h373 #define gpu_write(dev, reg, data) writel(data, dev->iomem + reg) macro
/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_iommu.c100 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, context->global->memory_base); in etnaviv_iommuv1_restore()
101 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, context->global->memory_base); in etnaviv_iommuv1_restore()
102 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, context->global->memory_base); in etnaviv_iommuv1_restore()
103 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, context->global->memory_base); in etnaviv_iommuv1_restore()
104 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, context->global->memory_base); in etnaviv_iommuv1_restore()
109 gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
110 gpu_write(gpu, VIVS_MC_MMU_TX_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
111 gpu_write(gpu, VIVS_MC_MMU_PE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
112 gpu_write(gpu, VIVS_MC_MMU_PEZ_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
113 gpu_write(gp in etnaviv_iommuv1_restore()
[all...]
H A Detnaviv_iommu_v2.c186 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
203 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW, in etnaviv_iommuv2_restore_sec()
205 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH, in etnaviv_iommuv2_restore_sec()
207 gpu_write(gpu, VIVS_MMUv2_PTA_CONTROL, VIVS_MMUv2_PTA_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
209 gpu_write(gpu, VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
211 gpu_write(gpu, VIVS_MMUv2_SEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
213 gpu_write(gpu, VIVS_MMUv2_SAFE_ADDRESS_CONFIG, in etnaviv_iommuv2_restore_sec()
228 gpu_write(gpu, VIVS_MMUv2_SEC_CONTROL, VIVS_MMUv2_SEC_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
H A Detnaviv_gpu.c501 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | in etnaviv_gpu_load_clock()
503 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in etnaviv_gpu_load_clock()
560 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
563 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, in etnaviv_hw_reset()
568 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
576 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
580 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
603 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
695 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); in etnaviv_gpu_start_fe()
696 gpu_write(gp in etnaviv_gpu_start_fe()
[all...]
H A Detnaviv_perfmon.c44 gpu_write(gpu, domain->profile_config, signal->data); in perf_reg_read()
54 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in pipe_select()
H A Detnaviv_sched.c59 gpu_write(gpu, VIVS_MC_PROFILE_CONFIG0, in etnaviv_sched_timedout_job()
H A Detnaviv_gpu.h170 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() function
/linux/drivers/gpu/drm/panthor/
H A Dpanthor_device.h399 gpu_write(ptdev, __reg_prefix ## _INT_MASK, 0); \
420 gpu_write(ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \
428 gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, 0); \
437 gpu_write(pirq->ptdev, __reg_prefix ## _INT_CLEAR, mask); \
438 gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, mask); \
458 static inline void gpu_write(struct panthor_device *ptdev, u32 reg, u32 data) in gpu_write() function
475 gpu_write(ptdev, reg, lower_32_bits(data)); in gpu_write64()
476 gpu_write(ptdev, reg + 4, upper_32_bits(data)); in gpu_write64()
H A Dpanthor_gpu.c82 gpu_write(ptdev, GPU_COHERENCY_PROTOCOL, in panthor_gpu_coherency_set()
148 gpu_write(ptdev, GPU_INT_CLEAR, status); in panthor_gpu_irq_handler()
360 gpu_write(ptdev, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other)); in panthor_gpu_flush_caches()
399 gpu_write(ptdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED); in panthor_gpu_soft_reset()
400 gpu_write(ptdev, GPU_CMD, GPU_SOFT_RESET); in panthor_gpu_soft_reset()
H A Dpanthor_fw.c1004 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); in panthor_fw_init_global_iface()
1013 gpu_write(ptdev, JOB_INT_CLEAR, status); in panthor_job_irq_handler()
1034 gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_AUTO); in panthor_fw_start()
1065 gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_DISABLE); in panthor_fw_stop()
1091 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); in panthor_fw_pre_reset()
1309 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); in panthor_fw_ring_csg_doorbells()
1324 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); in panthor_fw_ping_work()
H A Dpanthor_mmu.c532 gpu_write(ptdev, AS_COMMAND(as_nr), cmd); in write_cmd()
771 gpu_write(ptdev, MMU_INT_CLEAR, panthor_mmu_as_fault_mask(ptdev, as)); in panthor_vm_active()
774 gpu_write(ptdev, MMU_INT_MASK, ~ptdev->mmu->as.faulty_mask); in panthor_vm_active()
1695 gpu_write(ptdev, MMU_INT_CLEAR, mask); in panthor_mmu_irq_handler()
H A Dpanthor_sched.c3189 gpu_write(ptdev, CSF_DOORBELL(queue->doorbell_id), 1); in queue_run_job()
/linux/drivers/gpu/drm/i915/gem/selftests/
H A Dhuge_pages.c1055 static int gpu_write(struct intel_context *ce, in gpu_write() function
1175 err = gpu_write(ce, vma, dword, val); in __igt_write_huge()
1900 err = gpu_write(ce, vma, n++, 0xdeadbeaf); in igt_shrink_thp()