Lines Matching refs:gpu_write
89 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);
544 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1);
545 gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0);
548 gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1);
556 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0);
573 gpu_write(gpu, reg->offset, state ? reg->value : 0);
579 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
593 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL,
601 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), protect->regs[i]);
604 gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]);
703 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
710 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL,
715 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
722 gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL,
725 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL,
728 gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL,
1082 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);
1085 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, 0);
1088 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);
1091 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0);
1095 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
1106 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
1110 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1);
1111 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1);
1112 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1);
1113 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1);
1114 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1);
1115 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1);
1116 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1);
1117 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1);
1118 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1);
1119 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1);
1120 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);
1121 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
1132 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
1133 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
1134 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
1135 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
1136 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL,
1139 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
1143 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
1146 gpu_write(gpu, REG_A6XX_UCHE_GBIF_GX_CONFIG, 0x10240e0);
1149 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
1174 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, BIT(23));
1176 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
1177 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);
1181 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
1182 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
1184 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060);
1185 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16);
1187 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
1188 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
1192 gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
1196 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48);
1197 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47);
1199 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 64);
1200 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 63);
1202 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
1207 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL,
1211 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
1214 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1);
1223 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT);
1230 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff);
1232 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff);
1234 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff);
1236 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff);
1238 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff);
1240 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1);
1244 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
1245 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
1247 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
1249 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
1251 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
1267 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x00028801);
1269 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1);
1270 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);
1273 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(24));
1277 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x90);
1280 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906);
1282 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG,
1292 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
1294 gpu_write(gpu, REG_A7XX_CP_BV_APRIV_CNTL,
1296 gpu_write(gpu, REG_A7XX_CP_LPAC_APRIV_CNTL,
1299 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
1308 gpu_write(gpu, REG_A6XX_TPL1_DBG_ECO_CNTL1, 0xc0700);
1315 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK,
1332 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT);
1334 gpu_write(gpu, REG_A6XX_CP_RB_CNTL,
1360 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);
1395 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0);
1465 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3);
1659 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1);
1738 gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
1759 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status);
1875 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL1,
1883 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL0,
1992 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, GPR0_GBIF_HALT_REQUEST);
1996 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, VBIF_XIN_HALT_CTRL0_MASK);
1999 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
2006 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1);
2011 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
2016 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
2021 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
2030 gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert);