Lines Matching refs:gpu_write
123 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
124 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010);
125 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010);
126 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010);
127 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);
128 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010);
129 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010);
131 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff);
133 gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);
135 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);
136 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);
138 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x00181818);
139 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x00181818);
140 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000018);
141 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000018);
142 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x00000303);
143 gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
145 gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
146 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a);
147 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000a);
149 gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
150 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000010);
151 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000010);
154 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
155 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010);
156 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010);
157 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010);
158 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);
159 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010);
160 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010);
162 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff);
164 gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);
166 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);
167 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);
169 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x000000ff);
170 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
179 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f);
180 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
182 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003f);
183 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);
185 gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
189 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);
190 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x18181818);
191 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x18181818);
192 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x18181818);
193 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);
194 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x18181818);
195 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x18181818);
197 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003f);
199 gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);
201 gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0001);
203 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003f);
204 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003f003f);
206 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f);
207 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
211 gpu_write(gpu, REG_A3XX_VBIF_CLKON, 0x00000001);
218 gpu_write(gpu, REG_A3XX_RBBM_GPU_BUSY_MASKED, 0xffffffff);
221 gpu_write(gpu, REG_A3XX_RBBM_SP_HYST_CNT, 0x10);
222 gpu_write(gpu, REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10);
227 gpu_write(gpu, REG_A3XX_RBBM_AHB_CTL0, 0x00000001);
230 gpu_write(gpu, REG_A3XX_RBBM_AHB_CTL1, 0xa6ffffff);
233 gpu_write(gpu, REG_A3XX_RBBM_RBBM_CTL, 0x00030000);
238 gpu_write(gpu, REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL, 0x00010fff);
241 gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);
247 gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
249 gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);
251 gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
253 gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbffcffff);
256 gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x05515455);
258 gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x00000000);
262 gpu_write(gpu, REG_A3XX_RB_GMEM_BASE_ADDR,
267 gpu_write(gpu, REG_A3XX_RBBM_PERFCTR_CTL, 0x01);
272 gpu_write(gpu, perfcntr->select_reg, perfcntr->select_val);
275 gpu_write(gpu, REG_A3XX_RBBM_INT_0_MASK, A3XX_INT0_MASK);
285 gpu_write(gpu, REG_AXXX_CP_RB_CNTL,
289 gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));
292 gpu_write(gpu, REG_A3XX_CP_PROTECT_CTRL, 0x00000007);
295 gpu_write(gpu, REG_A3XX_CP_PROTECT(0), 0x63000040);
296 gpu_write(gpu, REG_A3XX_CP_PROTECT(1), 0x62000080);
297 gpu_write(gpu, REG_A3XX_CP_PROTECT(2), 0x600000cc);
298 gpu_write(gpu, REG_A3XX_CP_PROTECT(3), 0x60000108);
299 gpu_write(gpu, REG_A3XX_CP_PROTECT(4), 0x64000140);
300 gpu_write(gpu, REG_A3XX_CP_PROTECT(5), 0x66000400);
303 gpu_write(gpu, REG_A3XX_CP_PROTECT(6), 0x65000700);
304 gpu_write(gpu, REG_A3XX_CP_PROTECT(7), 0x610007d8);
305 gpu_write(gpu, REG_A3XX_CP_PROTECT(8), 0x620007e0);
306 gpu_write(gpu, REG_A3XX_CP_PROTECT(9), 0x61001178);
307 gpu_write(gpu, REG_A3XX_CP_PROTECT(10), 0x64001180);
310 gpu_write(gpu, REG_A3XX_CP_PROTECT(11), 0x60003300);
313 gpu_write(gpu, REG_A3XX_CP_PROTECT(12), 0x6b00c000);
326 gpu_write(gpu, REG_AXXX_CP_DEBUG,
329 gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0);
331 gpu_write(gpu, REG_AXXX_CP_ME_RAM_DATA, ptr[i]);
338 gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_ADDR, 0);
340 gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);
347 gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,
357 gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, 0x003e2008);
361 gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0);
381 gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 1);
383 gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 0);
428 gpu_write(gpu, REG_A3XX_RBBM_INT_CLEAR_CMD, status);