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/linux/drivers/irqchip/
H A Dirq-gic.c42 #include <linux/irqchip/arm-gic.h>
50 #include "irq-gic-common.h"
337 struct gic_chip_data *gic = &gic_data[0]; in gic_handle_irq() local
338 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq()
370 generic_handle_domain_irq(gic->domain, irqnr); in gic_handle_irq()
400 struct gic_chip_data *gic = irq_data_get_irq_chip_data(d); in gic_irq_print_chip() local
402 if (gic->domain->pm_dev) in gic_irq_print_chip()
403 seq_puts(p, gic->domain->pm_dev->of_node->name); in gic_irq_print_chip()
405 seq_printf(p, "GIC-%d", (int)(gic - &gic_data[0])); in gic_irq_print_chip()
415 static u8 gic_get_cpumask(struct gic_chip_data *gic) in gic_get_cpumask() argument
440 gic_cpu_if_up(struct gic_chip_data * gic) gic_cpu_if_up() argument
464 gic_dist_init(struct gic_chip_data * gic) gic_dist_init() argument
487 gic_cpu_init(struct gic_chip_data * gic) gic_cpu_init() argument
550 gic_dist_save(struct gic_chip_data * gic) gic_dist_save() argument
589 gic_dist_restore(struct gic_chip_data * gic) gic_dist_restore() argument
635 gic_cpu_save(struct gic_chip_data * gic) gic_cpu_save() argument
665 gic_cpu_restore(struct gic_chip_data * gic) gic_cpu_restore() argument
737 gic_pm_init(struct gic_chip_data * gic) gic_pm_init() argument
767 gic_pm_init(struct gic_chip_data * gic) gic_pm_init() argument
797 struct gic_chip_data *gic = irq_data_get_irq_chip_data(d); gic_set_affinity() local
1055 struct gic_chip_data *gic = d->host_data; gic_irq_domain_map() local
1163 gic_init_bases(struct gic_chip_data * gic,struct fwnode_handle * handle) gic_init_bases() argument
1238 __gic_init_bases(struct gic_chip_data * gic,struct fwnode_handle * handle) __gic_init_bases() argument
1267 gic_teardown(struct gic_chip_data * gic) gic_teardown() argument
1389 gic_of_setup(struct gic_chip_data * gic,struct device_node * node) gic_of_setup() argument
1415 gic_of_init_child(struct device * dev,struct gic_chip_data ** gic,int irq) gic_of_init_child() argument
1469 struct gic_chip_data *gic; gic_of_init() local
1638 struct gic_chip_data *gic = &gic_data[0]; gic_v2_acpi_init() local
[all...]
H A Dirq-gic-pm.c9 #include <linux/irqchip/arm-gic.h>
28 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_resume() local
42 if (!gic) in gic_runtime_resume()
45 gic_dist_restore(gic); in gic_runtime_resume()
46 gic_cpu_restore(gic); in gic_runtime_resume()
54 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_suspend() local
57 gic_dist_save(gic); in gic_runtime_suspend()
58 gic_cpu_save(gic); in gic_runtime_suspend()
154 .name = "gic",
H A DMakefile30 obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
31 obj-$(CONFIG_ARM_GIC_PM) += irq-gic-pm.o
32 obj-$(CONFIG_ARCH_REALVIEW) += irq-gic-realview.o
34 obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o
35 obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-v3-mbi.o irq-gic-common.o
36 obj-$(CONFIG_ARM_GIC_ITS_PARENT) += irq-gic-its-msi-parent.o
37 obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v4.o
38 obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC) += irq-gic-v3-its-fsl-mc-msi.o
40 obj-$(CONFIG_ARM_GIC_V5) += irq-gic-v5.o irq-gic-v5-irs.o irq-gic-v5-its.o \
41 irq-gic-v5-iwb.o
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Dfvp-base-revc.dts13 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
222 gic: interrupt-controller@2f000000 { label
223 compatible = "arm,gic-v3";
238 compatible = "arm,gic-v3-its";
338 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
339 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
340 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
341 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
375 interrupt-map = <0 0 0 &gic
[all...]
H A Dmorello-sdp.dts125 interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
126 <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>,
127 <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>,
128 <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>;
146 interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
147 <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>,
148 <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>,
149 <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>;
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-ns.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
75 gic: interrupt-controller@21000 { label
76 compatible = "arm,cortex-a9-gic";
106 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
109 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
110 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
111 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
112 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
113 <0x00007000 4 &gic GIC_SP
[all...]
H A Dbcm53573.dtsi9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
41 gic: interrupt-controller@1000 { label
42 compatible = "arm,cortex-a7-gic";
82 <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
85 <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
88 <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
89 <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
90 <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91 <0x00002000 3 &gic GIC_SP
[all...]
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2m-rs1.dtsi20 #include <dt-bindings/interrupt-controller/arm-gic.h>
111 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
112 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
113 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
114 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
115 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
116 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
117 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
118 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
119 <0 8 &gic GIC_SP
[all...]
H A Dvexpress-v2m.dtsi20 #include <dt-bindings/interrupt-controller/arm-gic.h>
32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
39 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
40 <0 8 &gic GIC_SP
[all...]
/linux/arch/arm64/boot/dts/cavium/
H A Dthunder2-99xx.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&gic>;
58 gic: interrupt-controller@4000080000 { label
59 compatible = "arm,gic-v3";
71 compatible = "arm,gic-v3-its";
120 <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
121 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
122 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
123 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
137 interrupt-parent = <&gic>;
[all...]
/linux/Documentation/devicetree/bindings/bus/
H A Dbrcm,bus-axi.txt34 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
37 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
40 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
41 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
42 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
43 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
44 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
45 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
/linux/arch/mips/boot/dts/mobileye/
H A Deyeq5.dtsi6 #include <dt-bindings/interrupt-controller/mips-gic.h>
116 interrupt-parent = <&gic>;
131 interrupt-parent = <&gic>;
146 interrupt-parent = <&gic>;
161 interrupt-parent = <&gic>;
176 interrupt-parent = <&gic>;
192 interrupt-parent = <&gic>;
205 interrupt-parent = <&gic>;
218 interrupt-parent = <&gic>;
236 gic label
[all...]
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi17 #include <dt-bindings/interrupt-controller/arm-gic.h>
147 interrupt-parent = <&gic>;
178 interrupt-parent = <&gic>;
209 interrupt-parent = <&gic>;
311 interrupt-parent = <&gic>;
508 interrupt-parent = <&gic>;
521 interrupt-parent = <&gic>;
539 interrupt-parent = <&gic>;
581 interrupt-parent = <&gic>;
594 interrupt-parent = <&gic>;
681 gic: interrupt-controller@f9010000 { global() label
[all...]
/linux/drivers/net/ethernet/microsoft/mana/
H A Dgdma_main.c630 struct gdma_irq_context *gic; in mana_gd_register_irq() local
650 gic = xa_load(&gc->irq_contexts, msi_index); in mana_gd_register_irq()
651 if (WARN_ON(!gic)) in mana_gd_register_irq()
654 spin_lock_irqsave(&gic->lock, flags); in mana_gd_register_irq()
655 list_add_rcu(&queue->entry, &gic->eq_list); in mana_gd_register_irq()
656 spin_unlock_irqrestore(&gic->lock, flags); in mana_gd_register_irq()
664 struct gdma_irq_context *gic; in mana_gd_deregister_irq() local
677 gic = xa_load(&gc->irq_contexts, msix_index); in mana_gd_deregister_irq()
678 if (WARN_ON(!gic)) in mana_gd_deregister_irq()
681 spin_lock_irqsave(&gic in mana_gd_deregister_irq()
1431 struct gdma_irq_context *gic = arg; mana_gd_intr() local
1544 struct gdma_irq_context *gic; mana_gd_setup_dyn_irqs() local
1625 struct gdma_irq_context *gic; mana_gd_setup_irqs() local
1779 struct gdma_irq_context *gic; mana_gd_remove_irqs() local
[all...]
/linux/arch/mips/boot/dts/ralink/
H A Dmt7621.dtsi2 #include <dt-bindings/interrupt-controller/mips-gic.h>
186 interrupt-parent = <&gic>;
223 interrupt-parent = <&gic>;
241 interrupt-parent = <&gic>;
261 interrupt-parent = <&gic>;
307 interrupt-parent = <&gic>;
334 interrupt-parent = <&gic>;
338 gic: interrupt-controller@1fbc0000 { label
339 compatible = "mti,gic";
348 compatible = "mti,gic
[all...]
/linux/arch/arm64/boot/dts/freescale/
H A Ds32v234.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
91 gic: interrupt-controller@7d001000 { label
92 compatible = "arm,cortex-a15-gic";
108 interrupt-parent = <&gic>;
115 interrupt-parent = <&gic>;
131 interrupt-parent = <&gic>;
/linux/arch/arm/boot/dts/samsung/
H A Dexynos54xx.dtsi30 interrupt-parent = <&gic>;
84 <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
85 <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
86 <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
87 <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
88 <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
89 <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
90 <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
91 <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
/linux/arch/mips/boot/dts/img/
H A Dboston.dts7 #include <dt-bindings/interrupt-controller/mips-gic.h>
48 interrupt-parent = <&gic>;
78 interrupt-parent = <&gic>;
108 interrupt-parent = <&gic>;
181 gic: interrupt-controller@16120000 { label
182 compatible = "mti,gic";
189 compatible = "mti,gic-timer";
227 interrupt-parent = <&gic>;
/linux/include/linux/irqchip/
H A Darm-gic.h3 * include/linux/irqchip/arm-gic.h
137 void gic_cpu_save(struct gic_chip_data *gic);
138 void gic_cpu_restore(struct gic_chip_data *gic);
139 void gic_dist_save(struct gic_chip_data *gic);
140 void gic_dist_restore(struct gic_chip_data *gic);
152 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq);
/linux/arch/mips/boot/dts/mti/
H A Dmalta.dts5 #include <dt-bindings/interrupt-controller/mips-gic.h>
23 gic: interrupt-controller@1bdc0000 { label
24 compatible = "mti,gic";
31 * Declare the interrupt-parent even though the mti,gic
39 compatible = "mti,gic-timer";
50 interrupt-parent = <&gic>;
/linux/arch/mips/include/asm/
H A Dmips-gic.h8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
31 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
32 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
36 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
37 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
41 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
42 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
46 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
47 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
/linux/tools/testing/selftests/kvm/arm64/
H A Dvgic_init.c824 static void test_sysreg_array(int gic, const struct sr_def *sr, int nr, in test_sysreg_array() argument
844 ret = __kvm_has_device_attr(gic, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, in test_sysreg_array()
849 ret = __kvm_device_attr_get(gic, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, in test_sysreg_array()
851 TEST_ASSERT(ret == 0 || !check(gic, &sr[i], "read"), "%s unreadable", sr[i].name); in test_sysreg_array()
852 ret = __kvm_device_attr_set(gic, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, in test_sysreg_array()
854 TEST_ASSERT(ret == 0 || !check(gic, &sr[i], "write"), "%s unwritable", sr[i].name); in test_sysreg_array()
858 static u8 get_ctlr_pribits(int gic) in get_ctlr_pribits() argument
864 ret = __kvm_device_attr_get(gic, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, in get_ctlr_pribits()
874 static int check_unaccessible_el1_regs(int gic, const struct sr_def *sr, const char *what) in check_unaccessible_el1_regs() argument
879 if (get_ctlr_pribits(gic) > in check_unaccessible_el1_regs()
897 get_vtr_pribits(int gic) get_vtr_pribits() argument
913 check_unaccessible_el2_regs(int gic,const struct sr_def * sr,const char * what) check_unaccessible_el2_regs() argument
942 int gic; test_v3_sysregs() local
[all...]
/linux/arch/arm/boot/dts/sunplus/
H A Dsunplus-sp7021-achip.dtsi9 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
48 gic: interrupt-controller@9f101000 { label
49 compatible = "arm,cortex-a7-gic";
79 interrupt-parent = <&gic>;
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap810-ap0.dtsi8 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&gic>;
46 interrupt-parent = <&gic>;
48 gic: interrupt-controller@3000000 { label
49 compatible = "arm,gic-v3";
64 compatible = "arm,gic-v3-its";
/linux/arch/arm64/boot/dts/apm/
H A Dapm-shadowcat.dtsi10 interrupt-parent = <&gic>;
120 gic: interrupt-controller@78090000 { label
121 compatible = "arm,cortex-a15-gic";
133 compatible = "arm,gic-v2m-frame";
138 compatible = "arm,gic-v2m-frame";
143 compatible = "arm,gic-v2m-frame";
148 compatible = "arm,gic-v2m-frame";
153 compatible = "arm,gic-v2m-frame";
158 compatible = "arm,gic-v2m-frame";
163 compatible = "arm,gic
[all...]

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