drivers/irqchip/irq-gic.c

42 #include <linux/irqchip/arm-gic.h>
50 #include "irq-gic-common.h"
337 	struct gic_chip_data *gic = &gic_data[0];
338 	void __iomem *cpu_base = gic_data_cpu_base(gic);
370 		generic_handle_domain_irq(gic->domain, irqnr);
400 	struct gic_chip_data *gic = irq_data_get_irq_chip_data(d);
402 	if (gic->domain->pm_dev)
403 		seq_puts(p, gic->domain->pm_dev->of_node->name);
405 		seq_printf(p, "GIC-%d", (int)(gic - &gic_data[0]));
415 static u8 gic_get_cpumask(struct gic_chip_data *gic)
417 	void __iomem *base = gic_data_dist_base(gic);
440 static void gic_cpu_if_up(struct gic_chip_data *gic)
442 	void __iomem *cpu_base = gic_data_cpu_base(gic);
447 	if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key))
464 static void gic_dist_init(struct gic_chip_data *gic)
468 	unsigned int gic_irqs = gic->gic_irqs;
469 	void __iomem *base = gic_data_dist_base(gic);
476 	cpumask = gic_get_cpumask(gic);
487 static int gic_cpu_init(struct gic_chip_data *gic)
489 	void __iomem *dist_base = gic_data_dist_base(gic);
490 	void __iomem *base = gic_data_cpu_base(gic);
499 	if (gic == &gic_data[0]) {
507 		cpu_mask = gic_get_cpumask(gic);
522 	gic_cpu_if_up(gic);
550 void gic_dist_save(struct gic_chip_data *gic)
556 	if (WARN_ON(!gic))
559 	gic_irqs = gic->gic_irqs;
560 	dist_base = gic_data_dist_base(gic);
566 		gic->saved_spi_conf[i] =
570 		gic->saved_spi_target[i] =
574 		gic->saved_spi_enable[i] =
578 		gic->saved_spi_active[i] =
589 void gic_dist_restore(struct gic_chip_data *gic)
595 	if (WARN_ON(!gic))
598 	gic_irqs = gic->gic_irqs;
599 	dist_base = gic_data_dist_base(gic);
607 		writel_relaxed(gic->saved_spi_conf[i],
615 		writel_relaxed(gic->saved_spi_target[i],
621 		writel_relaxed(gic->saved_spi_enable[i],
628 		writel_relaxed(gic->saved_spi_active[i],
635 void gic_cpu_save(struct gic_chip_data *gic)
642 	if (WARN_ON(!gic))
645 	dist_base = gic_data_dist_base(gic);
646 	cpu_base = gic_data_cpu_base(gic);
651 	ptr = raw_cpu_ptr(gic->saved_ppi_enable);
655 	ptr = raw_cpu_ptr(gic->saved_ppi_active);
659 	ptr = raw_cpu_ptr(gic->saved_ppi_conf);
665 void gic_cpu_restore(struct gic_chip_data *gic)
672 	if (WARN_ON(!gic))
675 	dist_base = gic_data_dist_base(gic);
676 	cpu_base = gic_data_cpu_base(gic);
681 	ptr = raw_cpu_ptr(gic->saved_ppi_enable);
688 	ptr = raw_cpu_ptr(gic->saved_ppi_active);
695 	ptr = raw_cpu_ptr(gic->saved_ppi_conf);
704 	gic_cpu_if_up(gic);
737 static int gic_pm_init(struct gic_chip_data *gic)
739 	gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
741 	if (WARN_ON(!gic->saved_ppi_enable))
744 	gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
746 	if (WARN_ON(!gic->saved_ppi_active))
749 	gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
751 	if (WARN_ON(!gic->saved_ppi_conf))
754 	if (gic == &gic_data[0])
760 	free_percpu(gic->saved_ppi_active);
762 	free_percpu(gic->saved_ppi_enable);
767 static int gic_pm_init(struct gic_chip_data *gic)
797 	struct gic_chip_data *gic = irq_data_get_irq_chip_data(d);
800 	if (unlikely(gic != &gic_data[0]))
865 				  "irqchip/arm/gic:starting",
1055 	struct gic_chip_data *gic = d->host_data;
1060 		gic == &gic_data[0]) ? &gic_chip_mode1 : &gic_chip;
1163 static int gic_init_bases(struct gic_chip_data *gic,
1168 	if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1172 		gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1173 		gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1174 		if (WARN_ON(!gic->dist_base.percpu_base ||
1175 			    !gic->cpu_base.percpu_base)) {
1183 			unsigned long offset = gic->percpu_offset * core_id;
1184 			*per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1185 				gic->raw_dist_base + offset;
1186 			*per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1187 				gic->raw_cpu_base + offset;
1193 		WARN(gic->percpu_offset,
1195 		     gic->percpu_offset);
1196 		gic->dist_base.common_base = gic->raw_dist_base;
1197 		gic->cpu_base.common_base = gic->raw_cpu_base;
1204 	gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1208 	gic->gic_irqs = gic_irqs;
1210 	gic->domain = irq_domain_create_linear(handle, gic_irqs,
1212 					       gic);
1213 	if (WARN_ON(!gic->domain)) {
1218 	gic_dist_init(gic);
1219 	ret = gic_cpu_init(gic);
1223 	ret = gic_pm_init(gic);
1230 	if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1231 		free_percpu(gic->dist_base.percpu_base);
1232 		free_percpu(gic->cpu_base.percpu_base);
1238 static int __init __gic_init_bases(struct gic_chip_data *gic,
1243 	if (WARN_ON(!gic || gic->domain))
1246 	if (gic == &gic_data[0]) {
1260 	ret = gic_init_bases(gic, handle);
1261 	if (gic == &gic_data[0])
1267 static void gic_teardown(struct gic_chip_data *gic)
1269 	if (WARN_ON(!gic))
1272 	if (gic->raw_dist_base)
1273 		iounmap(gic->raw_dist_base);
1274 	if (gic->raw_cpu_base)
1275 		iounmap(gic->raw_cpu_base);
1389 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1391 	if (!gic || !node)
1394 	gic->raw_dist_base = of_iomap(node, 0);
1395 	if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1398 	gic->raw_cpu_base = of_iomap(node, 1);
1399 	if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1402 	if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1403 		gic->percpu_offset = 0;
1405 	gic_enable_of_quirks(node, gic_quirks, gic);
1410 	gic_teardown(gic);
1415 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1419 	if (!dev || !dev->of_node || !gic || !irq)
1422 	*gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1423 	if (!*gic)
1426 	ret = gic_of_setup(*gic, dev->of_node);
1430 	ret = gic_init_bases(*gic, &dev->of_node->fwnode);
1432 		gic_teardown(*gic);
1436 	irq_domain_set_pm_device((*gic)->domain, dev);
1437 	irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1469 	struct gic_chip_data *gic;
1478 	gic = &gic_data[gic_cnt];
1480 	ret = gic_of_setup(gic, node);
1488 	if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
1491 	ret = __gic_init_bases(gic, &node->fwnode);
1493 		gic_teardown(gic);
1513 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1514 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1515 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1516 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1517 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1518 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1638 	struct gic_chip_data *gic = &gic_data[0];
1649 	gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1650 	if (!gic->raw_cpu_base) {
1656 	gic->raw_dist_base = ioremap(dist->base_address,
1658 	if (!gic->raw_dist_base) {
1660 		gic_teardown(gic);
1678 		gic_teardown(gic);
1682 	ret = __gic_init_bases(gic, gsi_domain_handle);
1686 		gic_teardown(gic);