1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright (c) 2021, Microsoft Corporation. */ 3 4 #include <linux/debugfs.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/utsname.h> 8 #include <linux/version.h> 9 10 #include <net/mana/mana.h> 11 12 struct dentry *mana_debugfs_root; 13 14 static u32 mana_gd_r32(struct gdma_context *g, u64 offset) 15 { 16 return readl(g->bar0_va + offset); 17 } 18 19 static u64 mana_gd_r64(struct gdma_context *g, u64 offset) 20 { 21 return readq(g->bar0_va + offset); 22 } 23 24 static void mana_gd_init_pf_regs(struct pci_dev *pdev) 25 { 26 struct gdma_context *gc = pci_get_drvdata(pdev); 27 void __iomem *sriov_base_va; 28 u64 sriov_base_off; 29 30 gc->db_page_size = mana_gd_r32(gc, GDMA_PF_REG_DB_PAGE_SIZE) & 0xFFFF; 31 gc->db_page_base = gc->bar0_va + 32 mana_gd_r64(gc, GDMA_PF_REG_DB_PAGE_OFF); 33 34 gc->phys_db_page_base = gc->bar0_pa + 35 mana_gd_r64(gc, GDMA_PF_REG_DB_PAGE_OFF); 36 37 sriov_base_off = mana_gd_r64(gc, GDMA_SRIOV_REG_CFG_BASE_OFF); 38 39 sriov_base_va = gc->bar0_va + sriov_base_off; 40 gc->shm_base = sriov_base_va + 41 mana_gd_r64(gc, sriov_base_off + GDMA_PF_REG_SHM_OFF); 42 } 43 44 static void mana_gd_init_vf_regs(struct pci_dev *pdev) 45 { 46 struct gdma_context *gc = pci_get_drvdata(pdev); 47 48 gc->db_page_size = mana_gd_r32(gc, GDMA_REG_DB_PAGE_SIZE) & 0xFFFF; 49 50 gc->db_page_base = gc->bar0_va + 51 mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET); 52 53 gc->phys_db_page_base = gc->bar0_pa + 54 mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET); 55 56 gc->shm_base = gc->bar0_va + mana_gd_r64(gc, GDMA_REG_SHM_OFFSET); 57 } 58 59 static void mana_gd_init_registers(struct pci_dev *pdev) 60 { 61 struct gdma_context *gc = pci_get_drvdata(pdev); 62 63 if (gc->is_pf) 64 mana_gd_init_pf_regs(pdev); 65 else 66 mana_gd_init_vf_regs(pdev); 67 } 68 69 static int mana_gd_query_max_resources(struct pci_dev *pdev) 70 { 71 struct gdma_context *gc = pci_get_drvdata(pdev); 72 struct gdma_query_max_resources_resp resp = {}; 73 struct gdma_general_req req = {}; 74 int err; 75 76 mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_MAX_RESOURCES, 77 sizeof(req), sizeof(resp)); 78 79 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 80 if (err || resp.hdr.status) { 81 dev_err(gc->dev, "Failed to query resource info: %d, 0x%x\n", 82 err, resp.hdr.status); 83 return err ? err : -EPROTO; 84 } 85 86 if (gc->num_msix_usable > resp.max_msix) 87 gc->num_msix_usable = resp.max_msix; 88 89 if (gc->num_msix_usable <= 1) 90 return -ENOSPC; 91 92 gc->max_num_queues = num_online_cpus(); 93 if (gc->max_num_queues > MANA_MAX_NUM_QUEUES) 94 gc->max_num_queues = MANA_MAX_NUM_QUEUES; 95 96 if (gc->max_num_queues > resp.max_eq) 97 gc->max_num_queues = resp.max_eq; 98 99 if (gc->max_num_queues > resp.max_cq) 100 gc->max_num_queues = resp.max_cq; 101 102 if (gc->max_num_queues > resp.max_sq) 103 gc->max_num_queues = resp.max_sq; 104 105 if (gc->max_num_queues > resp.max_rq) 106 gc->max_num_queues = resp.max_rq; 107 108 /* The Hardware Channel (HWC) used 1 MSI-X */ 109 if (gc->max_num_queues > gc->num_msix_usable - 1) 110 gc->max_num_queues = gc->num_msix_usable - 1; 111 112 return 0; 113 } 114 115 static int mana_gd_query_hwc_timeout(struct pci_dev *pdev, u32 *timeout_val) 116 { 117 struct gdma_context *gc = pci_get_drvdata(pdev); 118 struct gdma_query_hwc_timeout_resp resp = {}; 119 struct gdma_query_hwc_timeout_req req = {}; 120 int err; 121 122 mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_HWC_TIMEOUT, 123 sizeof(req), sizeof(resp)); 124 req.timeout_ms = *timeout_val; 125 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 126 if (err || resp.hdr.status) 127 return err ? err : -EPROTO; 128 129 *timeout_val = resp.timeout_ms; 130 131 return 0; 132 } 133 134 static int mana_gd_detect_devices(struct pci_dev *pdev) 135 { 136 struct gdma_context *gc = pci_get_drvdata(pdev); 137 struct gdma_list_devices_resp resp = {}; 138 struct gdma_general_req req = {}; 139 struct gdma_dev_id dev; 140 int found_dev = 0; 141 u16 dev_type; 142 int err; 143 u32 i; 144 145 mana_gd_init_req_hdr(&req.hdr, GDMA_LIST_DEVICES, sizeof(req), 146 sizeof(resp)); 147 148 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 149 if (err || resp.hdr.status) { 150 dev_err(gc->dev, "Failed to detect devices: %d, 0x%x\n", err, 151 resp.hdr.status); 152 return err ? err : -EPROTO; 153 } 154 155 for (i = 0; i < GDMA_DEV_LIST_SIZE && 156 found_dev < resp.num_of_devs; i++) { 157 dev = resp.devs[i]; 158 dev_type = dev.type; 159 160 /* Skip empty devices */ 161 if (dev.as_uint32 == 0) 162 continue; 163 164 found_dev++; 165 166 /* HWC is already detected in mana_hwc_create_channel(). */ 167 if (dev_type == GDMA_DEVICE_HWC) 168 continue; 169 170 if (dev_type == GDMA_DEVICE_MANA) { 171 gc->mana.gdma_context = gc; 172 gc->mana.dev_id = dev; 173 } else if (dev_type == GDMA_DEVICE_MANA_IB) { 174 gc->mana_ib.dev_id = dev; 175 gc->mana_ib.gdma_context = gc; 176 } 177 } 178 179 return gc->mana.dev_id.type == 0 ? -ENODEV : 0; 180 } 181 182 int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req, 183 u32 resp_len, void *resp) 184 { 185 struct hw_channel_context *hwc = gc->hwc.driver_data; 186 187 return mana_hwc_send_request(hwc, req_len, req, resp_len, resp); 188 } 189 EXPORT_SYMBOL_NS(mana_gd_send_request, "NET_MANA"); 190 191 int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 192 struct gdma_mem_info *gmi) 193 { 194 dma_addr_t dma_handle; 195 void *buf; 196 197 if (length < MANA_PAGE_SIZE || !is_power_of_2(length)) 198 return -EINVAL; 199 200 gmi->dev = gc->dev; 201 buf = dma_alloc_coherent(gmi->dev, length, &dma_handle, GFP_KERNEL); 202 if (!buf) 203 return -ENOMEM; 204 205 gmi->dma_handle = dma_handle; 206 gmi->virt_addr = buf; 207 gmi->length = length; 208 209 return 0; 210 } 211 212 void mana_gd_free_memory(struct gdma_mem_info *gmi) 213 { 214 dma_free_coherent(gmi->dev, gmi->length, gmi->virt_addr, 215 gmi->dma_handle); 216 } 217 218 static int mana_gd_create_hw_eq(struct gdma_context *gc, 219 struct gdma_queue *queue) 220 { 221 struct gdma_create_queue_resp resp = {}; 222 struct gdma_create_queue_req req = {}; 223 int err; 224 225 if (queue->type != GDMA_EQ) 226 return -EINVAL; 227 228 mana_gd_init_req_hdr(&req.hdr, GDMA_CREATE_QUEUE, 229 sizeof(req), sizeof(resp)); 230 231 req.hdr.dev_id = queue->gdma_dev->dev_id; 232 req.type = queue->type; 233 req.pdid = queue->gdma_dev->pdid; 234 req.doolbell_id = queue->gdma_dev->doorbell; 235 req.gdma_region = queue->mem_info.dma_region_handle; 236 req.queue_size = queue->queue_size; 237 req.log2_throttle_limit = queue->eq.log2_throttle_limit; 238 req.eq_pci_msix_index = queue->eq.msix_index; 239 240 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 241 if (err || resp.hdr.status) { 242 dev_err(gc->dev, "Failed to create queue: %d, 0x%x\n", err, 243 resp.hdr.status); 244 return err ? err : -EPROTO; 245 } 246 247 queue->id = resp.queue_index; 248 queue->eq.disable_needed = true; 249 queue->mem_info.dma_region_handle = GDMA_INVALID_DMA_REGION; 250 return 0; 251 } 252 253 static int mana_gd_disable_queue(struct gdma_queue *queue) 254 { 255 struct gdma_context *gc = queue->gdma_dev->gdma_context; 256 struct gdma_disable_queue_req req = {}; 257 struct gdma_general_resp resp = {}; 258 int err; 259 260 WARN_ON(queue->type != GDMA_EQ); 261 262 mana_gd_init_req_hdr(&req.hdr, GDMA_DISABLE_QUEUE, 263 sizeof(req), sizeof(resp)); 264 265 req.hdr.dev_id = queue->gdma_dev->dev_id; 266 req.type = queue->type; 267 req.queue_index = queue->id; 268 req.alloc_res_id_on_creation = 1; 269 270 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 271 if (err || resp.hdr.status) { 272 dev_err(gc->dev, "Failed to disable queue: %d, 0x%x\n", err, 273 resp.hdr.status); 274 return err ? err : -EPROTO; 275 } 276 277 return 0; 278 } 279 280 #define DOORBELL_OFFSET_SQ 0x0 281 #define DOORBELL_OFFSET_RQ 0x400 282 #define DOORBELL_OFFSET_CQ 0x800 283 #define DOORBELL_OFFSET_EQ 0xFF8 284 285 static void mana_gd_ring_doorbell(struct gdma_context *gc, u32 db_index, 286 enum gdma_queue_type q_type, u32 qid, 287 u32 tail_ptr, u8 num_req) 288 { 289 void __iomem *addr = gc->db_page_base + gc->db_page_size * db_index; 290 union gdma_doorbell_entry e = {}; 291 292 switch (q_type) { 293 case GDMA_EQ: 294 e.eq.id = qid; 295 e.eq.tail_ptr = tail_ptr; 296 e.eq.arm = num_req; 297 298 addr += DOORBELL_OFFSET_EQ; 299 break; 300 301 case GDMA_CQ: 302 e.cq.id = qid; 303 e.cq.tail_ptr = tail_ptr; 304 e.cq.arm = num_req; 305 306 addr += DOORBELL_OFFSET_CQ; 307 break; 308 309 case GDMA_RQ: 310 e.rq.id = qid; 311 e.rq.tail_ptr = tail_ptr; 312 e.rq.wqe_cnt = num_req; 313 314 addr += DOORBELL_OFFSET_RQ; 315 break; 316 317 case GDMA_SQ: 318 e.sq.id = qid; 319 e.sq.tail_ptr = tail_ptr; 320 321 addr += DOORBELL_OFFSET_SQ; 322 break; 323 324 default: 325 WARN_ON(1); 326 return; 327 } 328 329 /* Ensure all writes are done before ring doorbell */ 330 wmb(); 331 332 writeq(e.as_uint64, addr); 333 } 334 335 void mana_gd_wq_ring_doorbell(struct gdma_context *gc, struct gdma_queue *queue) 336 { 337 /* Hardware Spec specifies that software client should set 0 for 338 * wqe_cnt for Receive Queues. This value is not used in Send Queues. 339 */ 340 mana_gd_ring_doorbell(gc, queue->gdma_dev->doorbell, queue->type, 341 queue->id, queue->head * GDMA_WQE_BU_SIZE, 0); 342 } 343 EXPORT_SYMBOL_NS(mana_gd_wq_ring_doorbell, "NET_MANA"); 344 345 void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit) 346 { 347 struct gdma_context *gc = cq->gdma_dev->gdma_context; 348 349 u32 num_cqe = cq->queue_size / GDMA_CQE_SIZE; 350 351 u32 head = cq->head % (num_cqe << GDMA_CQE_OWNER_BITS); 352 353 mana_gd_ring_doorbell(gc, cq->gdma_dev->doorbell, cq->type, cq->id, 354 head, arm_bit); 355 } 356 EXPORT_SYMBOL_NS(mana_gd_ring_cq, "NET_MANA"); 357 358 static void mana_gd_process_eqe(struct gdma_queue *eq) 359 { 360 u32 head = eq->head % (eq->queue_size / GDMA_EQE_SIZE); 361 struct gdma_context *gc = eq->gdma_dev->gdma_context; 362 struct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr; 363 union gdma_eqe_info eqe_info; 364 enum gdma_eqe_type type; 365 struct gdma_event event; 366 struct gdma_queue *cq; 367 struct gdma_eqe *eqe; 368 u32 cq_id; 369 370 eqe = &eq_eqe_ptr[head]; 371 eqe_info.as_uint32 = eqe->eqe_info; 372 type = eqe_info.type; 373 374 switch (type) { 375 case GDMA_EQE_COMPLETION: 376 cq_id = eqe->details[0] & 0xFFFFFF; 377 if (WARN_ON_ONCE(cq_id >= gc->max_num_cqs)) 378 break; 379 380 cq = gc->cq_table[cq_id]; 381 if (WARN_ON_ONCE(!cq || cq->type != GDMA_CQ || cq->id != cq_id)) 382 break; 383 384 if (cq->cq.callback) 385 cq->cq.callback(cq->cq.context, cq); 386 387 break; 388 389 case GDMA_EQE_TEST_EVENT: 390 gc->test_event_eq_id = eq->id; 391 complete(&gc->eq_test_event); 392 break; 393 394 case GDMA_EQE_HWC_INIT_EQ_ID_DB: 395 case GDMA_EQE_HWC_INIT_DATA: 396 case GDMA_EQE_HWC_INIT_DONE: 397 case GDMA_EQE_HWC_SOC_SERVICE: 398 case GDMA_EQE_RNIC_QP_FATAL: 399 if (!eq->eq.callback) 400 break; 401 402 event.type = type; 403 memcpy(&event.details, &eqe->details, GDMA_EVENT_DATA_SIZE); 404 eq->eq.callback(eq->eq.context, eq, &event); 405 break; 406 407 default: 408 break; 409 } 410 } 411 412 static void mana_gd_process_eq_events(void *arg) 413 { 414 u32 owner_bits, new_bits, old_bits; 415 union gdma_eqe_info eqe_info; 416 struct gdma_eqe *eq_eqe_ptr; 417 struct gdma_queue *eq = arg; 418 struct gdma_context *gc; 419 struct gdma_eqe *eqe; 420 u32 head, num_eqe; 421 int i; 422 423 gc = eq->gdma_dev->gdma_context; 424 425 num_eqe = eq->queue_size / GDMA_EQE_SIZE; 426 eq_eqe_ptr = eq->queue_mem_ptr; 427 428 /* Process up to 5 EQEs at a time, and update the HW head. */ 429 for (i = 0; i < 5; i++) { 430 eqe = &eq_eqe_ptr[eq->head % num_eqe]; 431 eqe_info.as_uint32 = eqe->eqe_info; 432 owner_bits = eqe_info.owner_bits; 433 434 old_bits = (eq->head / num_eqe - 1) & GDMA_EQE_OWNER_MASK; 435 /* No more entries */ 436 if (owner_bits == old_bits) { 437 /* return here without ringing the doorbell */ 438 if (i == 0) 439 return; 440 break; 441 } 442 443 new_bits = (eq->head / num_eqe) & GDMA_EQE_OWNER_MASK; 444 if (owner_bits != new_bits) { 445 dev_err(gc->dev, "EQ %d: overflow detected\n", eq->id); 446 break; 447 } 448 449 /* Per GDMA spec, rmb is necessary after checking owner_bits, before 450 * reading eqe. 451 */ 452 rmb(); 453 454 mana_gd_process_eqe(eq); 455 456 eq->head++; 457 } 458 459 head = eq->head % (num_eqe << GDMA_EQE_OWNER_BITS); 460 461 mana_gd_ring_doorbell(gc, eq->gdma_dev->doorbell, eq->type, eq->id, 462 head, SET_ARM_BIT); 463 } 464 465 static int mana_gd_register_irq(struct gdma_queue *queue, 466 const struct gdma_queue_spec *spec) 467 { 468 struct gdma_dev *gd = queue->gdma_dev; 469 struct gdma_irq_context *gic; 470 struct gdma_context *gc; 471 unsigned int msi_index; 472 unsigned long flags; 473 struct device *dev; 474 int err = 0; 475 476 gc = gd->gdma_context; 477 dev = gc->dev; 478 msi_index = spec->eq.msix_index; 479 480 if (msi_index >= gc->num_msix_usable) { 481 err = -ENOSPC; 482 dev_err(dev, "Register IRQ err:%d, msi:%u nMSI:%u", 483 err, msi_index, gc->num_msix_usable); 484 485 return err; 486 } 487 488 queue->eq.msix_index = msi_index; 489 gic = &gc->irq_contexts[msi_index]; 490 491 spin_lock_irqsave(&gic->lock, flags); 492 list_add_rcu(&queue->entry, &gic->eq_list); 493 spin_unlock_irqrestore(&gic->lock, flags); 494 495 return 0; 496 } 497 498 static void mana_gd_deregiser_irq(struct gdma_queue *queue) 499 { 500 struct gdma_dev *gd = queue->gdma_dev; 501 struct gdma_irq_context *gic; 502 struct gdma_context *gc; 503 unsigned int msix_index; 504 unsigned long flags; 505 struct gdma_queue *eq; 506 507 gc = gd->gdma_context; 508 509 /* At most num_online_cpus() + 1 interrupts are used. */ 510 msix_index = queue->eq.msix_index; 511 if (WARN_ON(msix_index >= gc->num_msix_usable)) 512 return; 513 514 gic = &gc->irq_contexts[msix_index]; 515 spin_lock_irqsave(&gic->lock, flags); 516 list_for_each_entry_rcu(eq, &gic->eq_list, entry) { 517 if (queue == eq) { 518 list_del_rcu(&eq->entry); 519 break; 520 } 521 } 522 spin_unlock_irqrestore(&gic->lock, flags); 523 524 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 525 synchronize_rcu(); 526 } 527 528 int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq) 529 { 530 struct gdma_generate_test_event_req req = {}; 531 struct gdma_general_resp resp = {}; 532 struct device *dev = gc->dev; 533 int err; 534 535 mutex_lock(&gc->eq_test_event_mutex); 536 537 init_completion(&gc->eq_test_event); 538 gc->test_event_eq_id = INVALID_QUEUE_ID; 539 540 mana_gd_init_req_hdr(&req.hdr, GDMA_GENERATE_TEST_EQE, 541 sizeof(req), sizeof(resp)); 542 543 req.hdr.dev_id = eq->gdma_dev->dev_id; 544 req.queue_index = eq->id; 545 546 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 547 if (err) { 548 dev_err(dev, "test_eq failed: %d\n", err); 549 goto out; 550 } 551 552 err = -EPROTO; 553 554 if (resp.hdr.status) { 555 dev_err(dev, "test_eq failed: 0x%x\n", resp.hdr.status); 556 goto out; 557 } 558 559 if (!wait_for_completion_timeout(&gc->eq_test_event, 30 * HZ)) { 560 dev_err(dev, "test_eq timed out on queue %d\n", eq->id); 561 goto out; 562 } 563 564 if (eq->id != gc->test_event_eq_id) { 565 dev_err(dev, "test_eq got an event on wrong queue %d (%d)\n", 566 gc->test_event_eq_id, eq->id); 567 goto out; 568 } 569 570 err = 0; 571 out: 572 mutex_unlock(&gc->eq_test_event_mutex); 573 return err; 574 } 575 576 static void mana_gd_destroy_eq(struct gdma_context *gc, bool flush_evenets, 577 struct gdma_queue *queue) 578 { 579 int err; 580 581 if (flush_evenets) { 582 err = mana_gd_test_eq(gc, queue); 583 if (err) 584 dev_warn(gc->dev, "Failed to flush EQ: %d\n", err); 585 } 586 587 mana_gd_deregiser_irq(queue); 588 589 if (queue->eq.disable_needed) 590 mana_gd_disable_queue(queue); 591 } 592 593 static int mana_gd_create_eq(struct gdma_dev *gd, 594 const struct gdma_queue_spec *spec, 595 bool create_hwq, struct gdma_queue *queue) 596 { 597 struct gdma_context *gc = gd->gdma_context; 598 struct device *dev = gc->dev; 599 u32 log2_num_entries; 600 int err; 601 602 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 603 queue->id = INVALID_QUEUE_ID; 604 605 log2_num_entries = ilog2(queue->queue_size / GDMA_EQE_SIZE); 606 607 if (spec->eq.log2_throttle_limit > log2_num_entries) { 608 dev_err(dev, "EQ throttling limit (%lu) > maximum EQE (%u)\n", 609 spec->eq.log2_throttle_limit, log2_num_entries); 610 return -EINVAL; 611 } 612 613 err = mana_gd_register_irq(queue, spec); 614 if (err) { 615 dev_err(dev, "Failed to register irq: %d\n", err); 616 return err; 617 } 618 619 queue->eq.callback = spec->eq.callback; 620 queue->eq.context = spec->eq.context; 621 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 622 queue->eq.log2_throttle_limit = spec->eq.log2_throttle_limit ?: 1; 623 624 if (create_hwq) { 625 err = mana_gd_create_hw_eq(gc, queue); 626 if (err) 627 goto out; 628 629 err = mana_gd_test_eq(gc, queue); 630 if (err) 631 goto out; 632 } 633 634 return 0; 635 out: 636 dev_err(dev, "Failed to create EQ: %d\n", err); 637 mana_gd_destroy_eq(gc, false, queue); 638 return err; 639 } 640 641 static void mana_gd_create_cq(const struct gdma_queue_spec *spec, 642 struct gdma_queue *queue) 643 { 644 u32 log2_num_entries = ilog2(spec->queue_size / GDMA_CQE_SIZE); 645 646 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 647 queue->cq.parent = spec->cq.parent_eq; 648 queue->cq.context = spec->cq.context; 649 queue->cq.callback = spec->cq.callback; 650 } 651 652 static void mana_gd_destroy_cq(struct gdma_context *gc, 653 struct gdma_queue *queue) 654 { 655 u32 id = queue->id; 656 657 if (id >= gc->max_num_cqs) 658 return; 659 660 if (!gc->cq_table[id]) 661 return; 662 663 gc->cq_table[id] = NULL; 664 } 665 666 int mana_gd_create_hwc_queue(struct gdma_dev *gd, 667 const struct gdma_queue_spec *spec, 668 struct gdma_queue **queue_ptr) 669 { 670 struct gdma_context *gc = gd->gdma_context; 671 struct gdma_mem_info *gmi; 672 struct gdma_queue *queue; 673 int err; 674 675 queue = kzalloc(sizeof(*queue), GFP_KERNEL); 676 if (!queue) 677 return -ENOMEM; 678 679 gmi = &queue->mem_info; 680 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 681 if (err) { 682 dev_err(gc->dev, "GDMA queue type: %d, size: %u, gdma memory allocation err: %d\n", 683 spec->type, spec->queue_size, err); 684 goto free_q; 685 } 686 687 queue->head = 0; 688 queue->tail = 0; 689 queue->queue_mem_ptr = gmi->virt_addr; 690 queue->queue_size = spec->queue_size; 691 queue->monitor_avl_buf = spec->monitor_avl_buf; 692 queue->type = spec->type; 693 queue->gdma_dev = gd; 694 695 if (spec->type == GDMA_EQ) 696 err = mana_gd_create_eq(gd, spec, false, queue); 697 else if (spec->type == GDMA_CQ) 698 mana_gd_create_cq(spec, queue); 699 700 if (err) 701 goto out; 702 703 *queue_ptr = queue; 704 return 0; 705 out: 706 dev_err(gc->dev, "Failed to create queue type %d of size %u, err: %d\n", 707 spec->type, spec->queue_size, err); 708 mana_gd_free_memory(gmi); 709 free_q: 710 kfree(queue); 711 return err; 712 } 713 714 int mana_gd_destroy_dma_region(struct gdma_context *gc, u64 dma_region_handle) 715 { 716 struct gdma_destroy_dma_region_req req = {}; 717 struct gdma_general_resp resp = {}; 718 int err; 719 720 if (dma_region_handle == GDMA_INVALID_DMA_REGION) 721 return 0; 722 723 mana_gd_init_req_hdr(&req.hdr, GDMA_DESTROY_DMA_REGION, sizeof(req), 724 sizeof(resp)); 725 req.dma_region_handle = dma_region_handle; 726 727 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 728 if (err || resp.hdr.status) { 729 dev_err(gc->dev, "Failed to destroy DMA region: %d, 0x%x\n", 730 err, resp.hdr.status); 731 return -EPROTO; 732 } 733 734 return 0; 735 } 736 EXPORT_SYMBOL_NS(mana_gd_destroy_dma_region, "NET_MANA"); 737 738 static int mana_gd_create_dma_region(struct gdma_dev *gd, 739 struct gdma_mem_info *gmi) 740 { 741 unsigned int num_page = gmi->length / MANA_PAGE_SIZE; 742 struct gdma_create_dma_region_req *req = NULL; 743 struct gdma_create_dma_region_resp resp = {}; 744 struct gdma_context *gc = gd->gdma_context; 745 struct hw_channel_context *hwc; 746 u32 length = gmi->length; 747 size_t req_msg_size; 748 int err; 749 int i; 750 751 if (length < MANA_PAGE_SIZE || !is_power_of_2(length)) 752 return -EINVAL; 753 754 if (!MANA_PAGE_ALIGNED(gmi->virt_addr)) 755 return -EINVAL; 756 757 hwc = gc->hwc.driver_data; 758 req_msg_size = struct_size(req, page_addr_list, num_page); 759 if (req_msg_size > hwc->max_req_msg_size) 760 return -EINVAL; 761 762 req = kzalloc(req_msg_size, GFP_KERNEL); 763 if (!req) 764 return -ENOMEM; 765 766 mana_gd_init_req_hdr(&req->hdr, GDMA_CREATE_DMA_REGION, 767 req_msg_size, sizeof(resp)); 768 req->length = length; 769 req->offset_in_page = 0; 770 req->gdma_page_type = GDMA_PAGE_TYPE_4K; 771 req->page_count = num_page; 772 req->page_addr_list_len = num_page; 773 774 for (i = 0; i < num_page; i++) 775 req->page_addr_list[i] = gmi->dma_handle + i * MANA_PAGE_SIZE; 776 777 err = mana_gd_send_request(gc, req_msg_size, req, sizeof(resp), &resp); 778 if (err) 779 goto out; 780 781 if (resp.hdr.status || 782 resp.dma_region_handle == GDMA_INVALID_DMA_REGION) { 783 dev_err(gc->dev, "Failed to create DMA region: 0x%x\n", 784 resp.hdr.status); 785 err = -EPROTO; 786 goto out; 787 } 788 789 gmi->dma_region_handle = resp.dma_region_handle; 790 dev_dbg(gc->dev, "Created DMA region handle 0x%llx\n", 791 gmi->dma_region_handle); 792 out: 793 if (err) 794 dev_dbg(gc->dev, 795 "Failed to create DMA region of length: %u, page_type: %d, status: 0x%x, err: %d\n", 796 length, req->gdma_page_type, resp.hdr.status, err); 797 kfree(req); 798 return err; 799 } 800 801 int mana_gd_create_mana_eq(struct gdma_dev *gd, 802 const struct gdma_queue_spec *spec, 803 struct gdma_queue **queue_ptr) 804 { 805 struct gdma_context *gc = gd->gdma_context; 806 struct gdma_mem_info *gmi; 807 struct gdma_queue *queue; 808 int err; 809 810 if (spec->type != GDMA_EQ) 811 return -EINVAL; 812 813 queue = kzalloc(sizeof(*queue), GFP_KERNEL); 814 if (!queue) 815 return -ENOMEM; 816 817 gmi = &queue->mem_info; 818 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 819 if (err) { 820 dev_err(gc->dev, "GDMA queue type: %d, size: %u, gdma memory allocation err: %d\n", 821 spec->type, spec->queue_size, err); 822 goto free_q; 823 } 824 825 err = mana_gd_create_dma_region(gd, gmi); 826 if (err) 827 goto out; 828 829 queue->head = 0; 830 queue->tail = 0; 831 queue->queue_mem_ptr = gmi->virt_addr; 832 queue->queue_size = spec->queue_size; 833 queue->monitor_avl_buf = spec->monitor_avl_buf; 834 queue->type = spec->type; 835 queue->gdma_dev = gd; 836 837 err = mana_gd_create_eq(gd, spec, true, queue); 838 if (err) 839 goto out; 840 841 *queue_ptr = queue; 842 return 0; 843 out: 844 dev_err(gc->dev, "Failed to create queue type %d of size: %u, err: %d\n", 845 spec->type, spec->queue_size, err); 846 mana_gd_free_memory(gmi); 847 free_q: 848 kfree(queue); 849 return err; 850 } 851 EXPORT_SYMBOL_NS(mana_gd_create_mana_eq, "NET_MANA"); 852 853 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 854 const struct gdma_queue_spec *spec, 855 struct gdma_queue **queue_ptr) 856 { 857 struct gdma_context *gc = gd->gdma_context; 858 struct gdma_mem_info *gmi; 859 struct gdma_queue *queue; 860 int err; 861 862 if (spec->type != GDMA_CQ && spec->type != GDMA_SQ && 863 spec->type != GDMA_RQ) 864 return -EINVAL; 865 866 queue = kzalloc(sizeof(*queue), GFP_KERNEL); 867 if (!queue) 868 return -ENOMEM; 869 870 gmi = &queue->mem_info; 871 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 872 if (err) { 873 dev_err(gc->dev, "GDMA queue type: %d, size: %u, memory allocation err: %d\n", 874 spec->type, spec->queue_size, err); 875 goto free_q; 876 } 877 878 err = mana_gd_create_dma_region(gd, gmi); 879 if (err) 880 goto out; 881 882 queue->head = 0; 883 queue->tail = 0; 884 queue->queue_mem_ptr = gmi->virt_addr; 885 queue->queue_size = spec->queue_size; 886 queue->monitor_avl_buf = spec->monitor_avl_buf; 887 queue->type = spec->type; 888 queue->gdma_dev = gd; 889 890 if (spec->type == GDMA_CQ) 891 mana_gd_create_cq(spec, queue); 892 893 *queue_ptr = queue; 894 return 0; 895 out: 896 dev_err(gc->dev, "Failed to create queue type %d of size: %u, err: %d\n", 897 spec->type, spec->queue_size, err); 898 mana_gd_free_memory(gmi); 899 free_q: 900 kfree(queue); 901 return err; 902 } 903 EXPORT_SYMBOL_NS(mana_gd_create_mana_wq_cq, "NET_MANA"); 904 905 void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue) 906 { 907 struct gdma_mem_info *gmi = &queue->mem_info; 908 909 switch (queue->type) { 910 case GDMA_EQ: 911 mana_gd_destroy_eq(gc, queue->eq.disable_needed, queue); 912 break; 913 914 case GDMA_CQ: 915 mana_gd_destroy_cq(gc, queue); 916 break; 917 918 case GDMA_RQ: 919 break; 920 921 case GDMA_SQ: 922 break; 923 924 default: 925 dev_err(gc->dev, "Can't destroy unknown queue: type=%d\n", 926 queue->type); 927 return; 928 } 929 930 mana_gd_destroy_dma_region(gc, gmi->dma_region_handle); 931 mana_gd_free_memory(gmi); 932 kfree(queue); 933 } 934 EXPORT_SYMBOL_NS(mana_gd_destroy_queue, "NET_MANA"); 935 936 int mana_gd_verify_vf_version(struct pci_dev *pdev) 937 { 938 struct gdma_context *gc = pci_get_drvdata(pdev); 939 struct gdma_verify_ver_resp resp = {}; 940 struct gdma_verify_ver_req req = {}; 941 struct hw_channel_context *hwc; 942 int err; 943 944 hwc = gc->hwc.driver_data; 945 mana_gd_init_req_hdr(&req.hdr, GDMA_VERIFY_VF_DRIVER_VERSION, 946 sizeof(req), sizeof(resp)); 947 948 req.protocol_ver_min = GDMA_PROTOCOL_FIRST; 949 req.protocol_ver_max = GDMA_PROTOCOL_LAST; 950 951 req.gd_drv_cap_flags1 = GDMA_DRV_CAP_FLAGS1; 952 req.gd_drv_cap_flags2 = GDMA_DRV_CAP_FLAGS2; 953 req.gd_drv_cap_flags3 = GDMA_DRV_CAP_FLAGS3; 954 req.gd_drv_cap_flags4 = GDMA_DRV_CAP_FLAGS4; 955 956 req.drv_ver = 0; /* Unused*/ 957 req.os_type = 0x10; /* Linux */ 958 req.os_ver_major = LINUX_VERSION_MAJOR; 959 req.os_ver_minor = LINUX_VERSION_PATCHLEVEL; 960 req.os_ver_build = LINUX_VERSION_SUBLEVEL; 961 strscpy(req.os_ver_str1, utsname()->sysname, sizeof(req.os_ver_str1)); 962 strscpy(req.os_ver_str2, utsname()->release, sizeof(req.os_ver_str2)); 963 strscpy(req.os_ver_str3, utsname()->version, sizeof(req.os_ver_str3)); 964 965 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 966 if (err || resp.hdr.status) { 967 dev_err(gc->dev, "VfVerifyVersionOutput: %d, status=0x%x\n", 968 err, resp.hdr.status); 969 return err ? err : -EPROTO; 970 } 971 gc->pf_cap_flags1 = resp.pf_cap_flags1; 972 if (resp.pf_cap_flags1 & GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG) { 973 err = mana_gd_query_hwc_timeout(pdev, &hwc->hwc_timeout); 974 if (err) { 975 dev_err(gc->dev, "Failed to set the hwc timeout %d\n", err); 976 return err; 977 } 978 dev_dbg(gc->dev, "set the hwc timeout to %u\n", hwc->hwc_timeout); 979 } 980 return 0; 981 } 982 983 int mana_gd_register_device(struct gdma_dev *gd) 984 { 985 struct gdma_context *gc = gd->gdma_context; 986 struct gdma_register_device_resp resp = {}; 987 struct gdma_general_req req = {}; 988 int err; 989 990 gd->pdid = INVALID_PDID; 991 gd->doorbell = INVALID_DOORBELL; 992 gd->gpa_mkey = INVALID_MEM_KEY; 993 994 mana_gd_init_req_hdr(&req.hdr, GDMA_REGISTER_DEVICE, sizeof(req), 995 sizeof(resp)); 996 997 req.hdr.dev_id = gd->dev_id; 998 999 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1000 if (err || resp.hdr.status) { 1001 dev_err(gc->dev, "gdma_register_device_resp failed: %d, 0x%x\n", 1002 err, resp.hdr.status); 1003 return err ? err : -EPROTO; 1004 } 1005 1006 gd->pdid = resp.pdid; 1007 gd->gpa_mkey = resp.gpa_mkey; 1008 gd->doorbell = resp.db_id; 1009 1010 return 0; 1011 } 1012 1013 int mana_gd_deregister_device(struct gdma_dev *gd) 1014 { 1015 struct gdma_context *gc = gd->gdma_context; 1016 struct gdma_general_resp resp = {}; 1017 struct gdma_general_req req = {}; 1018 int err; 1019 1020 if (gd->pdid == INVALID_PDID) 1021 return -EINVAL; 1022 1023 mana_gd_init_req_hdr(&req.hdr, GDMA_DEREGISTER_DEVICE, sizeof(req), 1024 sizeof(resp)); 1025 1026 req.hdr.dev_id = gd->dev_id; 1027 1028 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1029 if (err || resp.hdr.status) { 1030 dev_err(gc->dev, "Failed to deregister device: %d, 0x%x\n", 1031 err, resp.hdr.status); 1032 if (!err) 1033 err = -EPROTO; 1034 } 1035 1036 gd->pdid = INVALID_PDID; 1037 gd->doorbell = INVALID_DOORBELL; 1038 gd->gpa_mkey = INVALID_MEM_KEY; 1039 1040 return err; 1041 } 1042 1043 u32 mana_gd_wq_avail_space(struct gdma_queue *wq) 1044 { 1045 u32 used_space = (wq->head - wq->tail) * GDMA_WQE_BU_SIZE; 1046 u32 wq_size = wq->queue_size; 1047 1048 WARN_ON_ONCE(used_space > wq_size); 1049 1050 return wq_size - used_space; 1051 } 1052 1053 u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset) 1054 { 1055 u32 offset = (wqe_offset * GDMA_WQE_BU_SIZE) & (wq->queue_size - 1); 1056 1057 WARN_ON_ONCE((offset + GDMA_WQE_BU_SIZE) > wq->queue_size); 1058 1059 return wq->queue_mem_ptr + offset; 1060 } 1061 1062 static u32 mana_gd_write_client_oob(const struct gdma_wqe_request *wqe_req, 1063 enum gdma_queue_type q_type, 1064 u32 client_oob_size, u32 sgl_data_size, 1065 u8 *wqe_ptr) 1066 { 1067 bool oob_in_sgl = !!(wqe_req->flags & GDMA_WR_OOB_IN_SGL); 1068 bool pad_data = !!(wqe_req->flags & GDMA_WR_PAD_BY_SGE0); 1069 struct gdma_wqe *header = (struct gdma_wqe *)wqe_ptr; 1070 u8 *ptr; 1071 1072 memset(header, 0, sizeof(struct gdma_wqe)); 1073 header->num_sge = wqe_req->num_sge; 1074 header->inline_oob_size_div4 = client_oob_size / sizeof(u32); 1075 1076 if (oob_in_sgl) { 1077 WARN_ON_ONCE(wqe_req->num_sge < 2); 1078 1079 header->client_oob_in_sgl = 1; 1080 1081 if (pad_data) 1082 header->last_vbytes = wqe_req->sgl[0].size; 1083 } 1084 1085 if (q_type == GDMA_SQ) 1086 header->client_data_unit = wqe_req->client_data_unit; 1087 1088 /* The size of gdma_wqe + client_oob_size must be less than or equal 1089 * to one Basic Unit (i.e. 32 bytes), so the pointer can't go beyond 1090 * the queue memory buffer boundary. 1091 */ 1092 ptr = wqe_ptr + sizeof(header); 1093 1094 if (wqe_req->inline_oob_data && wqe_req->inline_oob_size > 0) { 1095 memcpy(ptr, wqe_req->inline_oob_data, wqe_req->inline_oob_size); 1096 1097 if (client_oob_size > wqe_req->inline_oob_size) 1098 memset(ptr + wqe_req->inline_oob_size, 0, 1099 client_oob_size - wqe_req->inline_oob_size); 1100 } 1101 1102 return sizeof(header) + client_oob_size; 1103 } 1104 1105 static void mana_gd_write_sgl(struct gdma_queue *wq, u8 *wqe_ptr, 1106 const struct gdma_wqe_request *wqe_req) 1107 { 1108 u32 sgl_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1109 const u8 *address = (u8 *)wqe_req->sgl; 1110 u8 *base_ptr, *end_ptr; 1111 u32 size_to_end; 1112 1113 base_ptr = wq->queue_mem_ptr; 1114 end_ptr = base_ptr + wq->queue_size; 1115 size_to_end = (u32)(end_ptr - wqe_ptr); 1116 1117 if (size_to_end < sgl_size) { 1118 memcpy(wqe_ptr, address, size_to_end); 1119 1120 wqe_ptr = base_ptr; 1121 address += size_to_end; 1122 sgl_size -= size_to_end; 1123 } 1124 1125 memcpy(wqe_ptr, address, sgl_size); 1126 } 1127 1128 int mana_gd_post_work_request(struct gdma_queue *wq, 1129 const struct gdma_wqe_request *wqe_req, 1130 struct gdma_posted_wqe_info *wqe_info) 1131 { 1132 u32 client_oob_size = wqe_req->inline_oob_size; 1133 struct gdma_context *gc; 1134 u32 sgl_data_size; 1135 u32 max_wqe_size; 1136 u32 wqe_size; 1137 u8 *wqe_ptr; 1138 1139 if (wqe_req->num_sge == 0) 1140 return -EINVAL; 1141 1142 if (wq->type == GDMA_RQ) { 1143 if (client_oob_size != 0) 1144 return -EINVAL; 1145 1146 client_oob_size = INLINE_OOB_SMALL_SIZE; 1147 1148 max_wqe_size = GDMA_MAX_RQE_SIZE; 1149 } else { 1150 if (client_oob_size != INLINE_OOB_SMALL_SIZE && 1151 client_oob_size != INLINE_OOB_LARGE_SIZE) 1152 return -EINVAL; 1153 1154 max_wqe_size = GDMA_MAX_SQE_SIZE; 1155 } 1156 1157 sgl_data_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1158 wqe_size = ALIGN(sizeof(struct gdma_wqe) + client_oob_size + 1159 sgl_data_size, GDMA_WQE_BU_SIZE); 1160 if (wqe_size > max_wqe_size) 1161 return -EINVAL; 1162 1163 if (wq->monitor_avl_buf && wqe_size > mana_gd_wq_avail_space(wq)) { 1164 gc = wq->gdma_dev->gdma_context; 1165 dev_err(gc->dev, "unsuccessful flow control!\n"); 1166 return -ENOSPC; 1167 } 1168 1169 if (wqe_info) 1170 wqe_info->wqe_size_in_bu = wqe_size / GDMA_WQE_BU_SIZE; 1171 1172 wqe_ptr = mana_gd_get_wqe_ptr(wq, wq->head); 1173 wqe_ptr += mana_gd_write_client_oob(wqe_req, wq->type, client_oob_size, 1174 sgl_data_size, wqe_ptr); 1175 if (wqe_ptr >= (u8 *)wq->queue_mem_ptr + wq->queue_size) 1176 wqe_ptr -= wq->queue_size; 1177 1178 mana_gd_write_sgl(wq, wqe_ptr, wqe_req); 1179 1180 wq->head += wqe_size / GDMA_WQE_BU_SIZE; 1181 1182 return 0; 1183 } 1184 EXPORT_SYMBOL_NS(mana_gd_post_work_request, "NET_MANA"); 1185 1186 int mana_gd_post_and_ring(struct gdma_queue *queue, 1187 const struct gdma_wqe_request *wqe_req, 1188 struct gdma_posted_wqe_info *wqe_info) 1189 { 1190 struct gdma_context *gc = queue->gdma_dev->gdma_context; 1191 int err; 1192 1193 err = mana_gd_post_work_request(queue, wqe_req, wqe_info); 1194 if (err) { 1195 dev_err(gc->dev, "Failed to post work req from queue type %d of size %u (err=%d)\n", 1196 queue->type, queue->queue_size, err); 1197 return err; 1198 } 1199 1200 mana_gd_wq_ring_doorbell(gc, queue); 1201 1202 return 0; 1203 } 1204 1205 static int mana_gd_read_cqe(struct gdma_queue *cq, struct gdma_comp *comp) 1206 { 1207 unsigned int num_cqe = cq->queue_size / sizeof(struct gdma_cqe); 1208 struct gdma_cqe *cq_cqe = cq->queue_mem_ptr; 1209 u32 owner_bits, new_bits, old_bits; 1210 struct gdma_cqe *cqe; 1211 1212 cqe = &cq_cqe[cq->head % num_cqe]; 1213 owner_bits = cqe->cqe_info.owner_bits; 1214 1215 old_bits = (cq->head / num_cqe - 1) & GDMA_CQE_OWNER_MASK; 1216 /* Return 0 if no more entries. */ 1217 if (owner_bits == old_bits) 1218 return 0; 1219 1220 new_bits = (cq->head / num_cqe) & GDMA_CQE_OWNER_MASK; 1221 /* Return -1 if overflow detected. */ 1222 if (WARN_ON_ONCE(owner_bits != new_bits)) 1223 return -1; 1224 1225 /* Per GDMA spec, rmb is necessary after checking owner_bits, before 1226 * reading completion info 1227 */ 1228 rmb(); 1229 1230 comp->wq_num = cqe->cqe_info.wq_num; 1231 comp->is_sq = cqe->cqe_info.is_sq; 1232 memcpy(comp->cqe_data, cqe->cqe_data, GDMA_COMP_DATA_SIZE); 1233 1234 return 1; 1235 } 1236 1237 int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe) 1238 { 1239 int cqe_idx; 1240 int ret; 1241 1242 for (cqe_idx = 0; cqe_idx < num_cqe; cqe_idx++) { 1243 ret = mana_gd_read_cqe(cq, &comp[cqe_idx]); 1244 1245 if (ret < 0) { 1246 cq->head -= cqe_idx; 1247 return ret; 1248 } 1249 1250 if (ret == 0) 1251 break; 1252 1253 cq->head++; 1254 } 1255 1256 return cqe_idx; 1257 } 1258 EXPORT_SYMBOL_NS(mana_gd_poll_cq, "NET_MANA"); 1259 1260 static irqreturn_t mana_gd_intr(int irq, void *arg) 1261 { 1262 struct gdma_irq_context *gic = arg; 1263 struct list_head *eq_list = &gic->eq_list; 1264 struct gdma_queue *eq; 1265 1266 rcu_read_lock(); 1267 list_for_each_entry_rcu(eq, eq_list, entry) { 1268 gic->handler(eq); 1269 } 1270 rcu_read_unlock(); 1271 1272 return IRQ_HANDLED; 1273 } 1274 1275 int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r) 1276 { 1277 r->map = bitmap_zalloc(res_avail, GFP_KERNEL); 1278 if (!r->map) 1279 return -ENOMEM; 1280 1281 r->size = res_avail; 1282 spin_lock_init(&r->lock); 1283 1284 return 0; 1285 } 1286 1287 void mana_gd_free_res_map(struct gdma_resource *r) 1288 { 1289 bitmap_free(r->map); 1290 r->map = NULL; 1291 r->size = 0; 1292 } 1293 1294 static int irq_setup(unsigned int *irqs, unsigned int len, int node) 1295 { 1296 const struct cpumask *next, *prev = cpu_none_mask; 1297 cpumask_var_t cpus __free(free_cpumask_var); 1298 int cpu, weight; 1299 1300 if (!alloc_cpumask_var(&cpus, GFP_KERNEL)) 1301 return -ENOMEM; 1302 1303 rcu_read_lock(); 1304 for_each_numa_hop_mask(next, node) { 1305 weight = cpumask_weight_andnot(next, prev); 1306 while (weight > 0) { 1307 cpumask_andnot(cpus, next, prev); 1308 for_each_cpu(cpu, cpus) { 1309 if (len-- == 0) 1310 goto done; 1311 irq_set_affinity_and_hint(*irqs++, topology_sibling_cpumask(cpu)); 1312 cpumask_andnot(cpus, cpus, topology_sibling_cpumask(cpu)); 1313 --weight; 1314 } 1315 } 1316 prev = next; 1317 } 1318 done: 1319 rcu_read_unlock(); 1320 return 0; 1321 } 1322 1323 static int mana_gd_setup_irqs(struct pci_dev *pdev) 1324 { 1325 struct gdma_context *gc = pci_get_drvdata(pdev); 1326 unsigned int max_queues_per_port; 1327 struct gdma_irq_context *gic; 1328 unsigned int max_irqs, cpu; 1329 int start_irq_index = 1; 1330 int nvec, *irqs, irq; 1331 int err, i = 0, j; 1332 1333 cpus_read_lock(); 1334 max_queues_per_port = num_online_cpus(); 1335 if (max_queues_per_port > MANA_MAX_NUM_QUEUES) 1336 max_queues_per_port = MANA_MAX_NUM_QUEUES; 1337 1338 /* Need 1 interrupt for the Hardware communication Channel (HWC) */ 1339 max_irqs = max_queues_per_port + 1; 1340 1341 nvec = pci_alloc_irq_vectors(pdev, 2, max_irqs, PCI_IRQ_MSIX); 1342 if (nvec < 0) { 1343 cpus_read_unlock(); 1344 return nvec; 1345 } 1346 if (nvec <= num_online_cpus()) 1347 start_irq_index = 0; 1348 1349 irqs = kmalloc_array((nvec - start_irq_index), sizeof(int), GFP_KERNEL); 1350 if (!irqs) { 1351 err = -ENOMEM; 1352 goto free_irq_vector; 1353 } 1354 1355 gc->irq_contexts = kcalloc(nvec, sizeof(struct gdma_irq_context), 1356 GFP_KERNEL); 1357 if (!gc->irq_contexts) { 1358 err = -ENOMEM; 1359 goto free_irq_array; 1360 } 1361 1362 for (i = 0; i < nvec; i++) { 1363 gic = &gc->irq_contexts[i]; 1364 gic->handler = mana_gd_process_eq_events; 1365 INIT_LIST_HEAD(&gic->eq_list); 1366 spin_lock_init(&gic->lock); 1367 1368 if (!i) 1369 snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_hwc@pci:%s", 1370 pci_name(pdev)); 1371 else 1372 snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_q%d@pci:%s", 1373 i - 1, pci_name(pdev)); 1374 1375 irq = pci_irq_vector(pdev, i); 1376 if (irq < 0) { 1377 err = irq; 1378 goto free_irq; 1379 } 1380 1381 if (!i) { 1382 err = request_irq(irq, mana_gd_intr, 0, gic->name, gic); 1383 if (err) 1384 goto free_irq; 1385 1386 /* If number of IRQ is one extra than number of online CPUs, 1387 * then we need to assign IRQ0 (hwc irq) and IRQ1 to 1388 * same CPU. 1389 * Else we will use different CPUs for IRQ0 and IRQ1. 1390 * Also we are using cpumask_local_spread instead of 1391 * cpumask_first for the node, because the node can be 1392 * mem only. 1393 */ 1394 if (start_irq_index) { 1395 cpu = cpumask_local_spread(i, gc->numa_node); 1396 irq_set_affinity_and_hint(irq, cpumask_of(cpu)); 1397 } else { 1398 irqs[start_irq_index] = irq; 1399 } 1400 } else { 1401 irqs[i - start_irq_index] = irq; 1402 err = request_irq(irqs[i - start_irq_index], mana_gd_intr, 0, 1403 gic->name, gic); 1404 if (err) 1405 goto free_irq; 1406 } 1407 } 1408 1409 err = irq_setup(irqs, (nvec - start_irq_index), gc->numa_node); 1410 if (err) 1411 goto free_irq; 1412 1413 gc->max_num_msix = nvec; 1414 gc->num_msix_usable = nvec; 1415 cpus_read_unlock(); 1416 kfree(irqs); 1417 return 0; 1418 1419 free_irq: 1420 for (j = i - 1; j >= 0; j--) { 1421 irq = pci_irq_vector(pdev, j); 1422 gic = &gc->irq_contexts[j]; 1423 1424 irq_update_affinity_hint(irq, NULL); 1425 free_irq(irq, gic); 1426 } 1427 1428 kfree(gc->irq_contexts); 1429 gc->irq_contexts = NULL; 1430 free_irq_array: 1431 kfree(irqs); 1432 free_irq_vector: 1433 cpus_read_unlock(); 1434 pci_free_irq_vectors(pdev); 1435 return err; 1436 } 1437 1438 static void mana_gd_remove_irqs(struct pci_dev *pdev) 1439 { 1440 struct gdma_context *gc = pci_get_drvdata(pdev); 1441 struct gdma_irq_context *gic; 1442 int irq, i; 1443 1444 if (gc->max_num_msix < 1) 1445 return; 1446 1447 for (i = 0; i < gc->max_num_msix; i++) { 1448 irq = pci_irq_vector(pdev, i); 1449 if (irq < 0) 1450 continue; 1451 1452 gic = &gc->irq_contexts[i]; 1453 1454 /* Need to clear the hint before free_irq */ 1455 irq_update_affinity_hint(irq, NULL); 1456 free_irq(irq, gic); 1457 } 1458 1459 pci_free_irq_vectors(pdev); 1460 1461 gc->max_num_msix = 0; 1462 gc->num_msix_usable = 0; 1463 kfree(gc->irq_contexts); 1464 gc->irq_contexts = NULL; 1465 } 1466 1467 static int mana_gd_setup(struct pci_dev *pdev) 1468 { 1469 struct gdma_context *gc = pci_get_drvdata(pdev); 1470 int err; 1471 1472 mana_gd_init_registers(pdev); 1473 mana_smc_init(&gc->shm_channel, gc->dev, gc->shm_base); 1474 1475 gc->service_wq = alloc_ordered_workqueue("gdma_service_wq", 0); 1476 if (!gc->service_wq) 1477 return -ENOMEM; 1478 1479 err = mana_gd_setup_irqs(pdev); 1480 if (err) { 1481 dev_err(gc->dev, "Failed to setup IRQs: %d\n", err); 1482 goto free_workqueue; 1483 } 1484 1485 err = mana_hwc_create_channel(gc); 1486 if (err) 1487 goto remove_irq; 1488 1489 err = mana_gd_verify_vf_version(pdev); 1490 if (err) 1491 goto destroy_hwc; 1492 1493 err = mana_gd_query_max_resources(pdev); 1494 if (err) 1495 goto destroy_hwc; 1496 1497 err = mana_gd_detect_devices(pdev); 1498 if (err) 1499 goto destroy_hwc; 1500 1501 dev_dbg(&pdev->dev, "mana gdma setup successful\n"); 1502 return 0; 1503 1504 destroy_hwc: 1505 mana_hwc_destroy_channel(gc); 1506 remove_irq: 1507 mana_gd_remove_irqs(pdev); 1508 free_workqueue: 1509 destroy_workqueue(gc->service_wq); 1510 dev_err(&pdev->dev, "%s failed (error %d)\n", __func__, err); 1511 return err; 1512 } 1513 1514 static void mana_gd_cleanup(struct pci_dev *pdev) 1515 { 1516 struct gdma_context *gc = pci_get_drvdata(pdev); 1517 1518 mana_hwc_destroy_channel(gc); 1519 1520 mana_gd_remove_irqs(pdev); 1521 1522 destroy_workqueue(gc->service_wq); 1523 dev_dbg(&pdev->dev, "mana gdma cleanup successful\n"); 1524 } 1525 1526 static bool mana_is_pf(unsigned short dev_id) 1527 { 1528 return dev_id == MANA_PF_DEVICE_ID; 1529 } 1530 1531 static int mana_gd_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1532 { 1533 struct gdma_context *gc; 1534 void __iomem *bar0_va; 1535 int bar = 0; 1536 int err; 1537 1538 /* Each port has 2 CQs, each CQ has at most 1 EQE at a time */ 1539 BUILD_BUG_ON(2 * MAX_PORTS_IN_MANA_DEV * GDMA_EQE_SIZE > EQ_SIZE); 1540 1541 err = pci_enable_device(pdev); 1542 if (err) { 1543 dev_err(&pdev->dev, "Failed to enable pci device (err=%d)\n", err); 1544 return -ENXIO; 1545 } 1546 1547 pci_set_master(pdev); 1548 1549 err = pci_request_regions(pdev, "mana"); 1550 if (err) 1551 goto disable_dev; 1552 1553 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1554 if (err) { 1555 dev_err(&pdev->dev, "DMA set mask failed: %d\n", err); 1556 goto release_region; 1557 } 1558 dma_set_max_seg_size(&pdev->dev, UINT_MAX); 1559 1560 err = -ENOMEM; 1561 gc = vzalloc(sizeof(*gc)); 1562 if (!gc) 1563 goto release_region; 1564 1565 mutex_init(&gc->eq_test_event_mutex); 1566 pci_set_drvdata(pdev, gc); 1567 gc->bar0_pa = pci_resource_start(pdev, 0); 1568 1569 bar0_va = pci_iomap(pdev, bar, 0); 1570 if (!bar0_va) 1571 goto free_gc; 1572 1573 gc->numa_node = dev_to_node(&pdev->dev); 1574 gc->is_pf = mana_is_pf(pdev->device); 1575 gc->bar0_va = bar0_va; 1576 gc->dev = &pdev->dev; 1577 1578 if (gc->is_pf) 1579 gc->mana_pci_debugfs = debugfs_create_dir("0", mana_debugfs_root); 1580 else 1581 gc->mana_pci_debugfs = debugfs_create_dir(pci_slot_name(pdev->slot), 1582 mana_debugfs_root); 1583 1584 err = mana_gd_setup(pdev); 1585 if (err) 1586 goto unmap_bar; 1587 1588 err = mana_probe(&gc->mana, false); 1589 if (err) 1590 goto cleanup_gd; 1591 1592 err = mana_rdma_probe(&gc->mana_ib); 1593 if (err) 1594 goto cleanup_mana; 1595 1596 return 0; 1597 1598 cleanup_mana: 1599 mana_remove(&gc->mana, false); 1600 cleanup_gd: 1601 mana_gd_cleanup(pdev); 1602 unmap_bar: 1603 /* 1604 * at this point we know that the other debugfs child dir/files 1605 * are either not yet created or are already cleaned up. 1606 * The pci debugfs folder clean-up now, will only be cleaning up 1607 * adapter-MTU file and apc->mana_pci_debugfs folder. 1608 */ 1609 debugfs_remove_recursive(gc->mana_pci_debugfs); 1610 gc->mana_pci_debugfs = NULL; 1611 pci_iounmap(pdev, bar0_va); 1612 free_gc: 1613 pci_set_drvdata(pdev, NULL); 1614 vfree(gc); 1615 release_region: 1616 pci_release_regions(pdev); 1617 disable_dev: 1618 pci_disable_device(pdev); 1619 dev_err(&pdev->dev, "gdma probe failed: err = %d\n", err); 1620 return err; 1621 } 1622 1623 static void mana_gd_remove(struct pci_dev *pdev) 1624 { 1625 struct gdma_context *gc = pci_get_drvdata(pdev); 1626 1627 mana_rdma_remove(&gc->mana_ib); 1628 mana_remove(&gc->mana, false); 1629 1630 mana_gd_cleanup(pdev); 1631 1632 debugfs_remove_recursive(gc->mana_pci_debugfs); 1633 1634 gc->mana_pci_debugfs = NULL; 1635 1636 pci_iounmap(pdev, gc->bar0_va); 1637 1638 vfree(gc); 1639 1640 pci_release_regions(pdev); 1641 pci_disable_device(pdev); 1642 1643 dev_dbg(&pdev->dev, "mana gdma remove successful\n"); 1644 } 1645 1646 /* The 'state' parameter is not used. */ 1647 static int mana_gd_suspend(struct pci_dev *pdev, pm_message_t state) 1648 { 1649 struct gdma_context *gc = pci_get_drvdata(pdev); 1650 1651 mana_rdma_remove(&gc->mana_ib); 1652 mana_remove(&gc->mana, true); 1653 1654 mana_gd_cleanup(pdev); 1655 1656 return 0; 1657 } 1658 1659 /* In case the NIC hardware stops working, the suspend and resume callbacks will 1660 * fail -- if this happens, it's safer to just report an error than try to undo 1661 * what has been done. 1662 */ 1663 static int mana_gd_resume(struct pci_dev *pdev) 1664 { 1665 struct gdma_context *gc = pci_get_drvdata(pdev); 1666 int err; 1667 1668 err = mana_gd_setup(pdev); 1669 if (err) 1670 return err; 1671 1672 err = mana_probe(&gc->mana, true); 1673 if (err) 1674 return err; 1675 1676 err = mana_rdma_probe(&gc->mana_ib); 1677 if (err) 1678 return err; 1679 1680 return 0; 1681 } 1682 1683 /* Quiesce the device for kexec. This is also called upon reboot/shutdown. */ 1684 static void mana_gd_shutdown(struct pci_dev *pdev) 1685 { 1686 struct gdma_context *gc = pci_get_drvdata(pdev); 1687 1688 dev_info(&pdev->dev, "Shutdown was called\n"); 1689 1690 mana_rdma_remove(&gc->mana_ib); 1691 mana_remove(&gc->mana, true); 1692 1693 mana_gd_cleanup(pdev); 1694 1695 debugfs_remove_recursive(gc->mana_pci_debugfs); 1696 1697 gc->mana_pci_debugfs = NULL; 1698 1699 pci_disable_device(pdev); 1700 } 1701 1702 static const struct pci_device_id mana_id_table[] = { 1703 { PCI_DEVICE(PCI_VENDOR_ID_MICROSOFT, MANA_PF_DEVICE_ID) }, 1704 { PCI_DEVICE(PCI_VENDOR_ID_MICROSOFT, MANA_VF_DEVICE_ID) }, 1705 { } 1706 }; 1707 1708 static struct pci_driver mana_driver = { 1709 .name = "mana", 1710 .id_table = mana_id_table, 1711 .probe = mana_gd_probe, 1712 .remove = mana_gd_remove, 1713 .suspend = mana_gd_suspend, 1714 .resume = mana_gd_resume, 1715 .shutdown = mana_gd_shutdown, 1716 }; 1717 1718 static int __init mana_driver_init(void) 1719 { 1720 int err; 1721 1722 mana_debugfs_root = debugfs_create_dir("mana", NULL); 1723 1724 err = pci_register_driver(&mana_driver); 1725 if (err) { 1726 debugfs_remove(mana_debugfs_root); 1727 mana_debugfs_root = NULL; 1728 } 1729 1730 return err; 1731 } 1732 1733 static void __exit mana_driver_exit(void) 1734 { 1735 pci_unregister_driver(&mana_driver); 1736 1737 debugfs_remove(mana_debugfs_root); 1738 1739 mana_debugfs_root = NULL; 1740 } 1741 1742 module_init(mana_driver_init); 1743 module_exit(mana_driver_exit); 1744 1745 MODULE_DEVICE_TABLE(pci, mana_id_table); 1746 1747 MODULE_LICENSE("Dual BSD/GPL"); 1748 MODULE_DESCRIPTION("Microsoft Azure Network Adapter driver"); 1749