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Searched refs:dpll (Results 1 – 25 of 77) sorted by relevance

1234

/linux/drivers/dpll/
H A Ddpll_netlink.c16 #include <uapi/linux/dpll.h>
34 dpll_msg_add_dev_handle(struct sk_buff *msg, struct dpll_device *dpll) in dpll_msg_add_dev_handle() argument
36 if (nla_put_u32(msg, DPLL_A_ID, dpll->id)) in dpll_msg_add_dev_handle()
63 if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, in dpll_pin_available()
110 dpll_msg_add_mode(struct sk_buff *msg, struct dpll_device *dpll, in dpll_msg_add_mode() argument
113 const struct dpll_device_ops *ops = dpll_device_ops(dpll); in dpll_msg_add_mode()
117 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); in dpll_msg_add_mode()
127 dpll_msg_add_mode_supported(struct sk_buff *msg, struct dpll_device *dpll, in dpll_msg_add_mode_supported() argument
130 const struct dpll_device_ops *ops = dpll_device_ops(dpll); in dpll_msg_add_mode_supported()
148 dpll_msg_add_phase_offset_monitor(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_phase_offset_monitor() argument
168 dpll_msg_add_lock_status(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_lock_status() argument
192 dpll_msg_add_temp(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_temp() argument
211 dpll_msg_add_clock_quality_level(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_clock_quality_level() argument
237 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_prio() local
259 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_on_dpll_state() local
281 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_direction() local
301 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_phase_adjust() local
324 struct dpll_device *dpll = ref->dpll; dpll_msg_add_phase_offset() local
347 struct dpll_device *dpll = ref->dpll; dpll_msg_add_ffo() local
368 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_freq() local
409 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_esync() local
455 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_ref_sync() local
647 dpll_device_get_one(struct dpll_device * dpll,struct sk_buff * msg,struct netlink_ext_ack * extack) dpll_device_get_one() argument
685 dpll_device_event_send(enum dpll_cmd event,struct dpll_device * dpll) dpll_device_event_send() argument
715 dpll_device_create_ntf(struct dpll_device * dpll) dpll_device_create_ntf() argument
720 dpll_device_delete_ntf(struct dpll_device * dpll) dpll_device_delete_ntf() argument
726 __dpll_device_change_ntf(struct dpll_device * dpll) __dpll_device_change_ntf() argument
738 dpll_device_change_ntf(struct dpll_device * dpll) dpll_device_change_ntf() argument
818 dpll_phase_offset_monitor_set(struct dpll_device * dpll,struct nlattr * a,struct netlink_ext_ack * extack) dpll_phase_offset_monitor_set() argument
849 struct dpll_device *dpll; dpll_pin_freq_set() local
914 struct dpll_device *dpll; dpll_pin_esync_set() local
994 struct dpll_device *dpll; dpll_pin_ref_sync_state_set() local
1126 dpll_pin_state_set(struct dpll_device * dpll,struct dpll_pin * pin,enum dpll_pin_state state,struct netlink_ext_ack * extack) dpll_pin_state_set() argument
1154 dpll_pin_prio_set(struct dpll_device * dpll,struct dpll_pin * pin,u32 prio,struct netlink_ext_ack * extack) dpll_pin_prio_set() argument
1181 dpll_pin_direction_set(struct dpll_pin * pin,struct dpll_device * dpll,enum dpll_pin_direction direction,struct netlink_ext_ack * extack) dpll_pin_direction_set() argument
1215 struct dpll_device *dpll; dpll_pin_phase_adj_set() local
1288 struct dpll_device *dpll; dpll_pin_parent_device_set() local
1613 struct dpll_device *dpll_match = NULL, *dpll; dpll_device_find() local
1681 struct dpll_device *dpll; dpll_nl_device_id_get_doit() local
1711 struct dpll_device *dpll = info->user_ptr[0]; dpll_nl_device_get_doit() local
1737 dpll_set_from_nlattr(struct dpll_device * dpll,struct genl_info * info) dpll_set_from_nlattr() argument
1754 struct dpll_device *dpll = info->user_ptr[0]; dpll_nl_device_set_doit() local
1762 struct dpll_device *dpll; dpll_nl_device_get_dumpit() local
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H A Ddpll_core.c154 dpll_xa_ref_dpll_add(struct xarray *xa_dplls, struct dpll_device *dpll, in dpll_xa_ref_dpll_add() argument
164 if (ref->dpll != dpll) in dpll_xa_ref_dpll_add()
179 ref->dpll = dpll; in dpll_xa_ref_dpll_add()
181 ret = xa_insert(xa_dplls, dpll->id, ref, GFP_KERNEL); in dpll_xa_ref_dpll_add()
192 xa_erase(xa_dplls, dpll->id); in dpll_xa_ref_dpll_add()
208 dpll_xa_ref_dpll_del(struct xarray *xa_dplls, struct dpll_device *dpll, in dpll_xa_ref_dpll_del() argument
216 if (ref->dpll != dpll) in dpll_xa_ref_dpll_del()
245 struct dpll_device *dpll; dpll_device_alloc() local
284 struct dpll_device *dpll, *ret = NULL; dpll_device_get() local
313 dpll_device_put(struct dpll_device * dpll) dpll_device_put() argument
329 dpll_device_registration_find(struct dpll_device * dpll,const struct dpll_device_ops * ops,void * priv) dpll_device_registration_find() argument
355 dpll_device_register(struct dpll_device * dpll,enum dpll_type type,const struct dpll_device_ops * ops,void * priv) dpll_device_register() argument
410 dpll_device_unregister(struct dpll_device * dpll,const struct dpll_device_ops * ops,void * priv) dpll_device_unregister() argument
609 __dpll_pin_register(struct dpll_device * dpll,struct dpll_pin * pin,const struct dpll_pin_ops * ops,void * priv,void * cookie) __dpll_pin_register() argument
643 dpll_pin_register(struct dpll_device * dpll,struct dpll_pin * pin,const struct dpll_pin_ops * ops,void * priv) dpll_pin_register() argument
680 __dpll_pin_unregister(struct dpll_device * dpll,struct dpll_pin * pin,const struct dpll_pin_ops * ops,void * priv,void * cookie) __dpll_pin_unregister() argument
701 dpll_pin_unregister(struct dpll_device * dpll,struct dpll_pin * pin,const struct dpll_pin_ops * ops,void * priv) dpll_pin_unregister() argument
832 dpll_device_registration_first(struct dpll_device * dpll) dpll_device_registration_first() argument
842 dpll_priv(struct dpll_device * dpll) dpll_priv() argument
850 dpll_device_ops(struct dpll_device * dpll) dpll_device_ops() argument
869 dpll_pin_on_dpll_priv(struct dpll_device * dpll,struct dpll_pin * pin) dpll_pin_on_dpll_priv() argument
[all...]
H A DMakefile6 obj-$(CONFIG_DPLL) += dpll.o
7 dpll-y += dpll_core.o
8 dpll-y += dpll_netlink.o
9 dpll-y += dpll_nl.o
H A Ddpll_core.h10 #include <linux/dpll.h>
19 * @id: unique id number for device given by dpll subsystem
21 * @clock_id: unique identifier (clock_id) of a dpll
23 * @type: type of a dpll
24 * @pin_refs: stores pins registered within a dpll
26 * @registration_list: list of registered ops and priv data of dpll owners
40 * struct dpll_pin - structure for a dpll pin
41 * @id: unique id number for pin given by dpll subsystem
66 * struct dpll_pin_ref - structure for referencing either dpll or pins
67 * @dpll
74 struct dpll_device *dpll; global() member
[all...]
H A Ddpll_netlink.h7 int dpll_device_create_ntf(struct dpll_device *dpll);
9 int dpll_device_delete_ntf(struct dpll_device *dpll);
H A DKconfig11 source "drivers/dpll/zl3073x/Kconfig"
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c318 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
331 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) in i9xx_dpll_compute_m() argument
333 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
336 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
349 static int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
362 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
380 if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) in i9xx_pll_refclk()
409 hw_state->dpll in i9xx_dpll_get_hw_state()
428 u32 dpll = hw_state->dpll; i9xx_crtc_clock_get() local
987 i9xx_dpll_compute_fp(const struct dpll * dpll) i9xx_dpll_compute_fp() argument
992 pnv_dpll_compute_fp(const struct dpll * dpll) pnv_dpll_compute_fp() argument
1007 u32 dpll; i9xx_dpll() local
1097 u32 dpll; i8xx_dpll() local
1250 ilk_needs_fb_cb_tune(const struct dpll * dpll,int factor) ilk_needs_fb_cb_tune() argument
1271 u32 dpll; ilk_dpll() local
1424 u32 dpll; vlv_dpll() local
1450 u32 dpll; chv_dpll() local
2202 vlv_force_pll_on(struct intel_display * display,enum pipe pipe,const struct dpll * dpll) vlv_force_pll_on() argument
[all...]
H A Dintel_dpll.h12 struct dpll;
24 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
25 u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
32 const struct dpll *dpll);
42 struct dpll *best_clock);
43 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
H A Dintel_dpll_mgr.c130 /* Copy dpll state */ in intel_atomic_duplicate_dpll_state()
269 mutex_lock(&display->dpll.lock); in intel_dpll_enable()
295 mutex_unlock(&display->dpll.lock); in intel_dpll_enable()
318 mutex_lock(&display->dpll.lock); in intel_dpll_disable()
341 mutex_unlock(&display->dpll.lock); in intel_dpll_disable()
507 * This is the dpll version of drm_atomic_helper_swap_state() since the
543 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state()
577 intel_de_write(display, PCH_DPLL(id), hw_state->dpll); in ibx_pch_dpll_enable()
588 intel_de_write(display, PCH_DPLL(id), hw_state->dpll); in ibx_pch_dpll_enable()
653 drm_printf(p, "dpll_hw_state: dpll in ibx_dump_hw_state()
[all...]
H A Dg4x_dp.h21 const struct dpll *vlv_get_dpll(struct intel_display *display);
28 static inline const struct dpll *vlv_get_dpll(struct intel_display *display) in vlv_get_dpll()
H A Dintel_dpll_mgr.h34 for ((__i) = 0; (__i) < (__display)->dpll.num_dpll && \
35 ((__pll) = &(__display)->dpll.dplls[(__i)]) ; (__i)++)
49 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
53 * @DPLL_ID_PRIVATE: non-shared dpll in use
184 u32 dpll; member
390 /* dpll functions */
/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c107 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
158 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
160 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
161 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
163 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
167 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
168 dpll |= in psb_intel_crtc_mode_set()
173 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
176 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
179 dpll | in psb_intel_crtc_mode_set()
310 u32 dpll; psb_intel_crtc_clock_get() local
[all...]
H A Doaktrail_crtc.c245 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
247 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
248 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
251 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
253 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
256 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
258 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
317 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
319 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
321 REG_READ_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
373 u32 dpll = 0, fp = 0, dspcntr, pipeconf; oaktrail_crtc_mode_set() local
[all...]
H A Dcdv_intel_display.c584 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
665 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
676 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
678 dpll |= DPLLB_MODE_LVDS; in cdv_intel_crtc_mode_set()
680 dpll |= DPLLB_MODE_DAC_SERIAL; */ in cdv_intel_crtc_mode_set()
681 /* dpll |= (2 << 11); */ in cdv_intel_crtc_mode_set()
722 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
723 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
758 dpll | in cdv_intel_crtc_mode_set()
842 u32 dpll; cdv_intel_crtc_clock_get() local
[all...]
H A Dgma_display.c223 temp = REG_READ(map->dpll); in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
229 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
230 REG_READ(map->dpll); in gma_crtc_dpms()
233 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
234 REG_READ(map->dpll); in gma_crtc_dpms()
311 temp = REG_READ(map->dpll); in gma_crtc_dpms()
313 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
314 REG_READ(map->dpll); in gma_crtc_dpms()
[all...]
H A Doaktrail_hdmi.c285 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local
294 /* Disable dpll if necessary */ in oaktrail_crtc_hdmi_mode_set()
295 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
296 if ((dpll & DPLL_PWRDN) == 0) { in oaktrail_crtc_hdmi_mode_set()
297 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
306 /* program and enable dpll */ in oaktrail_crtc_hdmi_mode_set()
311 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
312 dpll &= ~DPLL_PDIV_MASK; in oaktrail_crtc_hdmi_mode_set()
313 dpll &= ~(DPLL_PWRDN | DPLL_RESET); in oaktrail_crtc_hdmi_mode_set()
317 REG_WRITE(DPLL_CTRL, (dpll | (cloc in oaktrail_crtc_hdmi_mode_set()
[all...]
/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Ddpll.c4 #include <linux/dpll.h>
11 struct dpll_device *dpll; member
144 mlx5_dpll_device_lock_status_get(const struct dpll_device *dpll, void *priv, in mlx5_dpll_device_lock_status_get() argument
161 static int mlx5_dpll_device_mode_get(const struct dpll_device *dpll, in mlx5_dpll_device_mode_get() argument
198 static int mlx5_dpll_clock_quality_level_get(const struct dpll_device *dpll, in mlx5_dpll_clock_quality_level_get() argument
257 const struct dpll_device *dpll, in mlx5_dpll_pin_direction_get() argument
268 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_get() argument
286 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_set() argument
300 const struct dpll_device *dpll, void *dpll_priv, in mlx5_dpll_ffo_get() argument
352 dpll_device_change_ntf(mdpll->dpll); in mlx5_dpll_periodic_work()
[all...]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7xx-clocks.dtsi229 compatible = "ti,omap4-dpll-m4xen-clock";
235 dpll_abe_x2_ck: clock-dpll-abe-x2 {
237 compatible = "ti,omap4-dpll-x2-clock";
242 dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {
264 dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
276 dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
307 compatible = "ti,omap4-dpll-core-clock";
313 dpll_core_x2_ck: clock-dpll-core-x2 {
315 compatible = "ti,omap4-dpll-x2-clock";
320 dpll_core_h12x2_ck: clock-dpll
[all...]
H A Dam43xx-clocks.dtsi231 compatible = "ti,am3-dpll-core-clock";
237 dpll_core_x2_ck: clock-dpll-core-x2 {
239 compatible = "ti,am3-dpll-x2-clock";
244 dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
256 dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
268 dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
282 compatible = "ti,am3-dpll-clock";
288 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
311 compatible = "ti,am3-dpll-clock";
317 dpll_ddr_m2_ck: clock-dpll
[all...]
/linux/drivers/dpll/zl3073x/
H A Ddpll.c8 #include <linux/dpll.h>
20 #include "dpll.h"
30 * @dpll: DPLL the pin is registered to
44 struct zl3073x_dpll *dpll; member
90 const struct dpll_device *dpll, void *dpll_priv, in zl3073x_dpll_pin_direction_get() argument
158 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_esync_get() argument
224 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_esync_set() argument
277 const struct dpll_device *dpll, void *dpll_priv, in zl3073x_dpll_input_pin_ffo_get() argument
290 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_frequency_get() argument
312 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_frequency_set() argument
518 zl3073x_dpll_input_pin_phase_offset_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s64 * phase_offset,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_phase_offset_get() argument
594 zl3073x_dpll_input_pin_phase_adjust_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 * phase_adjust,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_phase_adjust_get() argument
634 zl3073x_dpll_input_pin_phase_adjust_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_phase_adjust_set() argument
823 zl3073x_dpll_input_pin_state_on_dpll_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_state_on_dpll_get() argument
836 zl3073x_dpll_input_pin_state_on_dpll_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state state,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_state_on_dpll_set() argument
909 zl3073x_dpll_input_pin_prio_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 * prio,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_prio_get() argument
921 zl3073x_dpll_input_pin_prio_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 prio,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_prio_set() argument
946 zl3073x_dpll_output_pin_esync_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,struct dpll_pin_esync * esync,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_esync_get() argument
1061 zl3073x_dpll_output_pin_esync_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 freq,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_esync_set() argument
1160 zl3073x_dpll_output_pin_frequency_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_frequency_get() argument
1249 zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_frequency_set() argument
1383 zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 * phase_adjust,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_phase_adjust_get() argument
1432 zl3073x_dpll_output_pin_phase_adjust_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_phase_adjust_set() argument
1491 zl3073x_dpll_output_pin_state_on_dpll_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_state_on_dpll_get() argument
1503 zl3073x_dpll_lock_status_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_lock_status * status,enum dpll_lock_status_error * status_error,struct netlink_ext_ack * extack) zl3073x_dpll_lock_status_get() argument
1553 zl3073x_dpll_mode_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_mode * mode,struct netlink_ext_ack * extack) zl3073x_dpll_mode_get() argument
1580 zl3073x_dpll_phase_offset_monitor_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_feature_state * state,struct netlink_ext_ack * extack) zl3073x_dpll_phase_offset_monitor_get() argument
1596 zl3073x_dpll_phase_offset_monitor_set(const struct dpll_device * dpll,void * dpll_priv,enum dpll_feature_state state,struct netlink_ext_ack * extack) zl3073x_dpll_phase_offset_monitor_set() argument
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/linux/arch/arm/mach-omap1/
H A Dsram.S36 strh r0, [r2] @ set dpll into bypass mode
41 strh r0, [r2] @ write new dpll value
49 lock: ldrh r4, [r2], #0 @ read back dpll value
52 tst r4, #1 << 0 @ dpll rate locked?
/linux/drivers/ata/
H A Dpata_hpt3x2n.c312 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
319 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
328 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
330 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
332 flags |= dpll; in hpt3x2n_qc_issue()
335 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
H A Dpata_hpt37x.c948 int dpll, adjust; in hpt37x_init_one() local
951 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; in hpt37x_init_one()
953 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; in hpt37x_init_one()
981 if (dpll == 3) in hpt37x_init_one()
987 MHz[clock_slot], MHz[dpll]); in hpt37x_init_one()
/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_crtc.c83 struct dpll_info *dpll, in rcar_du_dpll_divider() argument
147 dpll->n = n; in rcar_du_dpll_divider()
148 dpll->m = m; in rcar_du_dpll_divider()
149 dpll->fdpll = fdpll; in rcar_du_dpll_divider()
150 dpll->output = output; in rcar_du_dpll_divider()
162 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff); in rcar_du_dpll_divider()
217 struct dpll_info dpll in rcar_du_crtc_set_display_timing() local
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/linux/arch/arm64/boot/dts/sprd/
H A Dsharkl3.dtsi123 dpll: dpll@0 { label
124 compatible = "sprd,sc9863a-dpll";

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