Lines Matching refs:dpll

245 			temp = REG_READ_WITH_AUX(map->dpll, i);
247 				REG_WRITE_WITH_AUX(map->dpll, temp, i);
248 				REG_READ_WITH_AUX(map->dpll, i);
251 				REG_WRITE_WITH_AUX(map->dpll,
253 				REG_READ_WITH_AUX(map->dpll, i);
256 				REG_WRITE_WITH_AUX(map->dpll,
258 				REG_READ_WITH_AUX(map->dpll, i);
317 			temp = REG_READ_WITH_AUX(map->dpll, i);
319 				REG_WRITE_WITH_AUX(map->dpll,
321 				REG_READ_WITH_AUX(map->dpll, i);
373 	u32 dpll = 0, fp = 0, dspcntr, pipeconf;
503 	dpll = 0;		/*BIT16 = 0 for 100MHz reference */
527 	dpll |= DPLL_VGA_MODE_DIS;
530 	dpll |= DPLL_VCO_ENABLE;
533 		dpll |= DPLLA_MODE_LVDS;
535 		dpll |= DPLLB_MODE_DAC_SERIAL;
541 		dpll |= DPLL_DVO_HIGH_SPEED;
542 		dpll |=
550 		dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16;
552 		dpll |= (1 << (clock.p1 - 2)) << 17;
554 	dpll |= DPLL_VCO_ENABLE;
556 	if (dpll & DPLL_VCO_ENABLE) {
559 			REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i);
560 			REG_READ_WITH_AUX(map->dpll, i);
568 		REG_WRITE_WITH_AUX(map->dpll, dpll, i);
569 		REG_READ_WITH_AUX(map->dpll, i);
574 		REG_WRITE_WITH_AUX(map->dpll, dpll, i);
575 		REG_READ_WITH_AUX(map->dpll, i);