Lines Matching refs:dpll
584 u32 dpll = 0, dspcntr, pipeconf;
665 dpll = DPLL_VGA_MODE_DIS;
676 dpll |= DPLL_SYNCLOCK_ENABLE;
678 dpll |= DPLLB_MODE_LVDS;
680 dpll |= DPLLB_MODE_DAC_SERIAL; */
681 /* dpll |= (2 << 11); */
722 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
723 REG_READ(map->dpll);
758 dpll |= DPLL_VCO_ENABLE;
767 REG_WRITE(map->dpll,
768 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
769 REG_READ(map->dpll);
773 if (!(REG_READ(map->dpll) & DPLL_LOCK)) {
842 u32 dpll;
849 dpll = REG_READ(map->dpll);
850 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
857 dpll = p->dpll;
858 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
873 ffs((dpll &
878 dev_err(dev->dev, "PLL %d\n", dpll);
882 if ((dpll & PLL_REF_INPUT_MASK) ==
889 if (dpll & PLL_P1_DIVIDE_BY_TWO)
893 ((dpll &
897 if (dpll & PLL_P2_DIVIDE_BY_4)