Searched refs:XCHAL_NUM_DBREAK (Results 1 – 15 of 15) sorted by relevance
22 static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[XCHAL_NUM_DBREAK]);30 return XCHAL_NUM_DBREAK; in hw_breakpoint_slots() 96 * XCHAL_NUM_DBREAK are. Thus the switch. In case build breaks here in xtensa_wsr() 100 BUILD_BUG_ON(XCHAL_NUM_DBREAK > 2); in xtensa_wsr() 114 #if XCHAL_NUM_DBREAK > 0 in xtensa_wsr() 122 #if XCHAL_NUM_DBREAK > 1 in xtensa_wsr() 185 i = alloc_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp); in arch_install_hw_breakpoint() 224 i = free_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp); in arch_uninstall_hw_breakpoint() 245 for (i = 0; i < XCHAL_NUM_DBREAK; ++i) { in flush_ptrace_hw_breakpoint() 268 for (i = 0; i < XCHAL_NUM_DBREAK; in restore_dbreak() [all...]
377 for (i = 0; i < XCHAL_NUM_DBREAK; ++i) in ptrace_hbptriggered() 423 (dbreak && idx >= XCHAL_NUM_DBREAK)) in ptrace_gethbpregs() 459 (dbreak && idx >= XCHAL_NUM_DBREAK)) in ptrace_sethbpregs()
133 .rept XCHAL_NUM_DBREAK
647 XCHAL_NUM_DBREAK, in c_show()
866 .rept XCHAL_NUM_DBREAK884 .rept XCHAL_NUM_DBREAK
135 unsigned long dbreakc_save[XCHAL_NUM_DBREAK];
161 struct perf_event *ptrace_wp[XCHAL_NUM_DBREAK];
328 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
353 #define XCHAL_NUM_DBREAK 0 /* number of DBREAKn regs */ macro
393 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
443 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
489 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
532 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro
553 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ macro